Abstract: A bus interface interrupt arrangement is disclosed which provides separate interrupt controllers for each bus in a multibus computer system where the processor is connected to one of the busses. Interrupt requests decided on each of the busses other than a primary bus to which the processor is connected are input along with interrupts from circuits connected to the primary bus to the interrupt controller for the primary bus. The interrupt request decided by the interrupt controller for the primary bus is connected to an interrupt input of the processor. All interrupt controllers are connected to the primary bus and may be accessed by the processor. When an interrupt from one of the busses other than the primary bus is chosen by the processor, the processor must read the interrupt controllers to determine first what bus, and then identify the circuit that generated the interrupt that has been acknowledged.

Abstract: A synchronous latch device macrocell which includes an input gate section and a scannable latch section. Both sections are directly connected together to provide a non-inverting path for input data signals thereby eliminating the need for internal inverting buffer circuits. The non-inverting output of the latch section connects to an output pin and provides a signal representation of the state of the latch device. The output pin is externally connected through a conductor wire to either one of a pair of complementary data input pins of the input gate section. The connection made is selected as a function of which data input pin connection provides the faster loading of the latch device as viewed from the source of the signal applied to the load control pin of the input gate section.

Abstract: A separate register file memory is included in at least two units of a pipelined processor which are located on separate integrated circuit chips. The register file memories of the units are interconnected so as to share certain input data register stages to enable updating to take place within a minimum of time. Each unit has a microprogrammed control unit which automatically provides update commands during the unit's cycles of operation. The signals from each microprogrammed control unit are applied to both register file memories enabling both memories to be updated during successive cycles of operation and thereby function collectively as one unit. This ensures that both units have access to the same most recently updated user visible information enabling both units to complete the execution of different instructions entering pipeline.

Abstract: A dual port read/write register file memory includes means for performing a read/modify write cycle of operation within a single system cycle of operation. The register file memory is constructed from one to more (RAM) addressable multibit storage arrays organized to form a dual read port, single write port RAM. Additionally, the register file includes a plurality of clocked input registers arranged in pairs for storing command, address and data signals for two write ports. The different pairs of registers are connected as inputs to a first set of multiplexer circuits whose outputs connect to the write control signal, address and data inputs of the single write port. The single write port of the register file memory is enabled for writing twice during each cycle. This allows data clocked into the input registers during the previous cycle to be written sequentially into the register file storage locations.

Abstract: A logic control system is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system to a CPU without compromising memory bandwidths or CPU execution speeds because of transfer delays or timing variances. Instruction modifications and plural task assignments are accommodated during instruction execution.

Abstract: A logic control system is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system to a CPU without compromising memory bandwidths or CPU execution speeds because of transfer delays or timing variances. Instruction modifications and plural task assignments are accommodated during instruction execution.

Abstract: A logic control system comprised of a cache memory system and a transfer control logic unit is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system on a common communication bus to a CPU. The CPU and the transfer control logic unit communicate by way of the cache memory system with the common communication bus. In response to a CPU request to the central memory system, procedural information and instructions are requested by the transfer control logic unit from the cache memory system and presented to the CPU in such a manner as to avoid interruptions in CPU activity caused by information transfer delays.

Abstract: This disclosure relates to a control system for transferring binary words from a memory system. One thirty two bit double word may be loaded into a selected two of four sixteen bit registers. As a first of the two selected registers is read, another thirty two bit word may be loaded into the unselected registers. Alternatively, sixteen bit single words may be loaded into and read from the registers. When a word has procedural information, it is read from the registers onto a CPU control bus via a multiplexer. When a word is an encoded computer instruction to the CPU, it is read from the registers into a logic unit via a multiplexer. A decoded instruction from the logic unit is read onto a CPU control bus.

Abstract: A data processing system includes a memory subsystem for storing operands and instructions and a central processing unit (CPU) for manipulating the operands by executing the instructions. The CPU includes a control store for generating signals for controlling the CPU operation. Shifters made up of multiplexers shift operands between an outer bus and a write bus in response to control store signals. The multiplexers shift the operands left or right 1, 2 or 4-bit positions including open shifts and circular shifts and also perform byte position shifting and twinning.

Abstract: A technique and apparatus for storing data and addressing stored data in a memory from which multiple words of data are to be retrieved in parallel is disclosed. The memory is addressed by providing the address of the first of N consecutive words to be retrieved in parallel. The data is stored in memory in physical data words which contain N logical data words such that the addressing of one physical data word will result in N logical data words being read in parallel from the memory. Each physical data word contains the contents of the logical data word having the same address as that of the physical data word in its leftmost position followed in the next right position by the contents of the logical data word having the next higher address, and so on until the rightmost position of the physical data word contains the contents of the logical data word with an address equal to the physical data word address plus N-1.

Abstract: A control store included in a data processing system for storing microinstructions in a plurality of microinstructions storage locations is organized in two parts, an upper bank and a lower bank. The lower bank is directly addressed by a portion of the currently addressed control store word, whereas the upper bank is addressed by use of a multiplexer, with inputs thereto coupled from various logic elements. Apparatus is included to determine which part of the control store will be selected and to allow such determination at a time substantially after the addresses for the first and second parts have been received by the control store.

Abstract: In a data processing system, a central processor unit requests procedural data words or non-procedural data words stored in the system memory. A control store device executes firmware instructions including a local bus field for controlling the transfer of the requested procedural data words and non-procedural data words to the central processor unit.

Abstract: A first bank or a second bank of storage locations of a control store of a data processing system is enabled in response to one of a plurality of test signals received as parallel inputs by two multiplexer devices. Only one of the multiplexers is enabled at a given time in response to the polarity of one of the test signals selected from the inputs of the multiplexer devices.

Abstract: A data processing system includes a first memory for storing microinstructions in a first plurality of storage locations and second memory for storing microinstructions in a second plurality of storage locations. A central processor executing a series of addressed microinstructions to control the functions performed by this system generates the address of the next microinstruction to be executed in series as well as a next address selection signal. Addressing circuitry concurrently applies the next address generated by the processor to address inputs of each of the first memory and the second memory. After a predetermined delay, either the first memory or the second memory is selected to output an address microinstruction responsive to the value of the next address selection signal.

Abstract: In a data processing system, a central subsystem includes a plurality of special purpose processing units with one of the processing units serving as a control processing unit within a central subsystem. The processing units are coupled to a common subsystem bus for the transfer of data, control information, and address information within the central subsystem. Access to the subsystem bus is allocated by a bus control unit which also interfaces the central subsystem with other processing units such as a system memory or system I/O devices that are included in the data processing system.

Abstract: A Scientific Instruction Processor (SIP) uses a Programmable Read Only Memory (PROM) to control the output of a two stage shifter. The shifter performs the necessary mantissa shift operations of shift right, shift left, shift right around, as well as inserting certain constant information into the system. Control signals and shift signals applied to the input address terminals of the PROM select the PROM output signals which enable the selected mantissa hexadecimal digits which output the shifter. This forces hexadecimal digits from the enabled positions and hexadecimal ZERO digits in those positions not enabled.

Abstract: A scientific processing unit includes a microprogrammable arithmetic processing apparatus for performing floating point arithmetic operations with operands in long and short form. The apparatus includes a microprogrammable control section and a plurality of microprocessor arithmetic and logic unit chip stages organized into two sections and carry look-ahead circuits coupled thereto. One section includes a predetermined number of series-coupled stages connected to process exponent values or long mantissa values. The other section includes another predetermined number of series coupled stages connected to process short mantissa values. Control circuits interconnect the stages of both sections and connect to the carry look-ahead circuits and to the microprogrammed control section.

Abstract: A scientific processing unit includes apparatus for performing floating point multiplication operations with operands in binary coded form. The apparatus is constructed from standard multibit LSI microprocessor chips organized into a number of vertical slices. Each chip includes an arithmetic logic unit (ALU) and a random access memory (RAM). The ALU's are used to generate a predetermined number of submultiples of a mantissa portion of a floating point number which are stored in the chips memories. The submultiples are generated by multiplying the mantissa by predetermined factors which correspond to the values of multiplier digit positions selected during the multiplication operation.The apparatus further includes selection circuits which provide for selection of the least significant bit positions from each of a number of groups of multiplier digits during the multiplication operation.