Abstract: An MPEG audio/video decoder has memories, a signal processing unit (SPU) including a multiplier and a butterfly unit, a main CPU, and a memory controller which are time division multiplexed between decoding video and audio data. For audio decoding, the butterfly unit determines combinations of components of a frequency-domain vector to reduce the number of multiplies required to transform to the time domain (matrixing). Matrixing is interwoven with MPEG filtering to increase throughput of the decoder by increasing parallel use of the multiplier, the butterfly unit, and a memory controller. A widowing process for the MPEG standard uses only independent components of the audio vectors. This reduces the required number of components to be stored, thereby reducing the size of required memory, the time to write the components after matrixing, and the time to retrieve the components for windowing.

Abstract: A decoder for compressed video signals comprises a central processing unit (CPU), a dynamic random access memory (DRAM) controller, a variable length code (VLC) decoder, a pixel filter and a video output unit. The microcoded CPU performs dequantization and inverse cosine transform using a pipelined data path, which includes both general purpose and special purpose hardware. In one embodiment, the VLC decoder is implemented as a table-driven state machine where the table contains both control information and decoded values.

Abstract: An MPEG audio/video decoder has memories, a signal processing unit (SPU) including a multiplier and a butterfly unit, a main CPU, and a memory controller which are time division multiplexed between decoding video and audio data. For audio decoding, the butterfly unit determines combinations of components of a frequency-domain vector to reduce the number of multiplies required to transform to the time domain (matrixing). Matrixing is interwoven with MPEG filtering to increase throughput of the decoder by increasing parallel use of the multiplier, the butterfly unit, and a memory controller.

Abstract: A method and structure including four video decompression structures and eight memory banks are provided for decoding high definition television (HDTV) signal. In this HDTV decompression structure, the 1920.times.1080 pixel display space is divided into four vertical sections of 480.times.1080 pixels. Each memory bank stores the values of pixels in one non-overlapping group of 240.times.1080 pixels. Each decompression structure decodes a 480.times.1088-pixel picture area with access to up to two additional 240.times.1088-pixel picture areas. The video decompression structures decode the vertical sections in lock-step to avoid the problem of the same bank of memory being accessed by more than one video decompression structure. In one embodiment of the present invention, a macroblock fetch can cross 1-4 DRAM page boundaries. So, in order to maintain the lock-step relationship of the video decompression structures, each page mode access is limited to fetching only an 8.times.

Abstract: A motion compensation structure and a method are provided for decoding interframe coded video data using motion vectors. The motion compensation structure includes a filter for resampling the pixel data in both vertical and horizontal directions, a prediction memory structure and a weighted adder structure. In one embodiment of the present invention, a weighted adder structure and a method are provided for performing bilinear interpolation of two values using multiplexers and an multiple-input adder.

Abstract: An MPEG audio/video decoder has memories, a signal processing unit (SPU) including a multiplier and a butterfly unit, a main CPU, and a memory controller which are time division multiplexed between decoding video and audio data. The decoder includes a degrouping circuit which performs two divisions in three clock cycles to degroup a subband code. Three cycles matches the write time of three components so that subband codes are degrouped and written to memory with a minimum delay. Performing two divides in three clock cycles allows the divider to be smaller and the decoder to be less expensive.

Abstract: In response to an error signal from a source of an MPEG audio data stream, a decoder replaces data with an error code and temporarily enables error handling. The error code is a valid bit combination rarely found in MPEG audio data frames. During audio decoding with error handling enabled, the decoder checks for the error code and replaces the error code with reconstructed data. Typically, some subband data are replaced with zeros so that an error only changes some of the frequency components.

Abstract: An MPEG audio/video decoder has memories, a signal processing unit (SPU) including a multiplier and a butterfly unit, a main CPU, and a memory controller which are time division multiplexed between decoding video and audio data. For audio decoding, the butterfly unit determines combinations of components of a frequency-domain vector to reduce the number of multiplies required to transform to the time domain (matrixing). Matrixing is interwoven with MPEG filtering to increases throughput of the decoder by increasing parallel use of the multiplier, the butterfly unit, and a memory controller. The decoder includes a degrouping circuit which performs two divisions in three clock cycles to degroup a subband code. Three cycles matches the write time of three components so that subband codes are degrouped and written to memory with a minimum delay. Performing two divides in three clock cycles allows the divider to be smaller.

Abstract: A 2-dimensional display space is mapped into the external DRAM addresses by embedding in the address space X and Y vectors of the display space. The mapping of the X and Y vectors allows a macroblock of pixels to be stored in one DRAM memory page, so that an access to a macroblock can be efficiently accomplished under a page mode access to the DRAM page. By providing control to one address bit, data of four pixels can be obtained at one time in one of 2 pixel.times.2 pixel "quad pixel" configuration, or in a 4 pixel.times.1 pixel horizontal "scan" configuration. In addition, a structure and a method are provided for accessing a 16.times.16-pixel picture area in two parts, in order that the number of DRAM page boundaries crossed during access of the 16.times.16-pixel picture area is minimized, thereby increasing the efficiency of memory access by reducing the overhead cost of initial accesses under page mode access to DRAMs.

Abstract: A method and a structure are provided to decode intra-frame and interframe coded compressed video data. In one embodiment of the present invention, a decompression structure having a processor is provided with a global bus over which a decoder coprocessor, an inverse discrete cosine transform coprocessor and a motion compensation coprocessor communicate. The decompression structure in accordance with the present invention communicates with a host computer over a host bus and with an external dynamic random access memory over a memory bus. The processor in the decompression structure of the present invention provides overall control to the decoder, IDCT and motion compensation coprocessors by reading and writing into a plurality of data and control registers, each register associated with one of the decoder, the IDCT and the motion compensation coprocessors.

Abstract: A separate data stream allows encoding of an overlay image, which is to be superimposed on images of a video sequence. The pixels of the overlay image can be transparent or have a text color, a shadow color, or an intermediate color either between the text color and the shadow color, or between the shadow color and the color of the corresponding pixel in the underlying video image. The intermediate colors provide for antialiasing. In addition, a color selection circuit allows selection of the next color from a pool of 9 colors, using a 3-bit field.

Abstract: A method and a structure are provided to decode intraframe and interframe coded compressed video data. In one embodiment, a decompression structure having a processor is provided with a global bus over which a decoder coprocessor, an inverse discrete cosine transform coprocessor and a motion compensation coprocessor communicate. The decompression structure communicates with a host computer over a host bus and with an external dynamic random access memory over a memory bus. The processor provides overall control to the coprocessors by reading and writing into a plurality of data and control registers, each register associated with one of the coprocessors. A structure including four of the decompression structures and a method are provided for decoding high definition television (HDTV) signals. In this structure for decoding HDTV signals, each decompression structure decodes a 480.times.1088-pixel picture area with access to up to two additional 240.times.1088-pixel picture areas.