Patents by Inventor David E. Grider

David E. Grider has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7514759
    Abstract: A process for fabricating a combined micro electromechanical/gallium nitride structure. The micro electromechanical structure comprises a piezoelectric device, such as a piezoelectric switch or a bulk acoustic wave device. According to the process, high Q compact bulk acoustic wave resonators can be built. The process is applicable to technologies such as tunable planar filter technology, amplifier technology and high speed analog-to-digital converters.
    Type: Grant
    Filed: April 11, 2005
    Date of Patent: April 7, 2009
    Assignee: HRL Laboratories, LLC
    Inventors: Sarabjit Mehta, David E. Grider, Wah S. Wong
  • Patent number: 7247893
    Abstract: A method for fabricating a non-planar heterostructure field effect transistor using group III-nitride materials with consistent repeatable results is disclosed. The method provides a substrate on which at least one layer of semiconductor material is deposited. An AlN layer is deposited on the at least one layer of semiconductor material. A portion of the AlN layer is removed using a solvent to create a non-planar region with consistent and repeatable results. The at least one layer beneath the AlN layer is insoluble in the solvent and therefore acts as an etch stop, preventing any damage to the at least one layer beneath the AlN layer. Furthermore, should the AlN layer incur any surface damage as a result of the reactive ion etching, the damage will be removed when exposed to the solvent to create the non-planar region.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: July 24, 2007
    Assignee: HRL Laboratories, LLC
    Inventors: Jeong Sun Moon, Paul Hashimoto, Wah S. Wong, David E. Grider
  • Patent number: 6830945
    Abstract: A method for fabricating a non-planar heterostructure field effect transistor using group III-nitride materials with consistent repeatable results is disclosed. The method provides a substrate on which at least one layer of semiconductor material is deposited. An AlN layer is deposited on the at least one layer of semiconductor material. A portion of the AlN layer is removed using a solvent to create a non-planar region with consistent and repeatable results. The at least one layer beneath the AlN layer is insoluble in the solvent and therefore acts as an etch stop, preventing any damage to the at least one layer beneath the AlN layer. Furthermore, should the AlN layer incur any surface damage as a result of the reactive ion etching, the damage will be removed when exposed to the solvent to create the non-planar region.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: December 14, 2004
    Assignee: HRL Laboratories, LLC
    Inventors: Jeong Sun Moon, Paul Hashimoto, Wah S. Wong, David E. Grider
  • Publication number: 20040051112
    Abstract: A method for fabricating a non-planar heterostructure field effect transistor using group III-nitride materials with consistent repeatable results is disclosed. The method provides a substrate on which at least one layer of semiconductor material is deposited. An AlN layer is deposited on the at least one layer of semiconductor material. A portion of the AlN layer is removed using a solvent to create a non-planar region with consistent and repeatable results. The at least one layer beneath the AlN layer is insoluble in the solvent and therefore acts as an etch stop, preventing any damage to the at least one layer beneath the AlN layer. Furthermore, should the AlN layer incur any surface damage as a result of the reactive ion etching, the damage will be removed when exposed to the solvent to create the non-planar region.
    Type: Application
    Filed: March 12, 2003
    Publication date: March 18, 2004
    Applicant: HRL LABORATORIES, LLC
    Inventors: Jeong Sun Moon, Paul Hashimoto, Wah S. Wong, David E. Grider
  • Patent number: 5298772
    Abstract: A monolithic integrated circuit device combines integrated heterostructure acoustic charge transport (HACT) devices and heterostructure insulated gate field effect transistor (HIGFET) devices in a single structure in which the HACT and HIGFET layers are grown in as a contiguous composite heterostructure.
    Type: Grant
    Filed: February 28, 1992
    Date of Patent: March 29, 1994
    Assignee: Honeywell Inc.
    Inventors: Andrzej Peczalski, David E. Grider, James F. Detry, George A. Kilgore, William J. Tanski, Thomas W. Grudkowski, Robert N. Sacks