Patents by Inventor David E. Hart

David E. Hart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9070714
    Abstract: Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a second body region formed proximal to the first surface. Moreover, each body region includes a source region formed therein. The substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to function as a drift region between the drain region and the source regions. A dual-gate is formed over the first surface of the substrate. The dual-gate includes a first gate region and a second gate region that define a gap there between to reduce the gate to drain capacitance. A conductive layer may be formed over the first gate region and the second gate region to lower the effective resistance of the dual-gate.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: June 30, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Scott J. Alberhasky, David E. Hart, Sudarsan Uppili
  • Patent number: 8643067
    Abstract: Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a second body region formed proximal to the first surface. Moreover, each body region includes a source region formed therein. The substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to function as a drift region between the drain region and the source regions. A dual-gate is formed over the first surface of the substrate. The dual-gate includes a first gate region and a second gate region that define a gap there between to reduce the gate to drain capacitance. A conductive layer may be formed over the first gate region and the second gate region to lower the effective resistance of the dual-gate.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: February 4, 2014
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Scott J. Alberhasky, David E. Hart, Sudarsan Uppili
  • Publication number: 20130082320
    Abstract: Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a second body region formed proximal to the first surface. Moreover, each body region includes a source region formed therein. The substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to function as a drift region between the drain region and the source regions. A dual-gate is formed over the first surface of the substrate. The dual-gate includes a first gate region and a second gate region that define a gap there between to reduce the gate to drain capacitance. A conductive layer may be formed over the first gate region and the second gate region to lower the effective resistance of the dual-gate.
    Type: Application
    Filed: September 30, 2011
    Publication date: April 4, 2013
    Applicant: Maxim Integrated Products, Inc.
    Inventors: Scott J. Alberhasky, David E. Hart, Sudarsan Uppili