Patents by Inventor David E. Holden

David E. Holden has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Spacer layer for electrophoretic display device
    Patent number: 7123238
    Abstract: An electrophoretic display device includes a spacer layer sandwiched between two conductive film substrates, the spacer layer defining a multiplicity of individual reservoirs within the display device which are filled with a display liquid.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: October 17, 2006
    Assignee: Xerox Corporation
    Inventors: Pinyen Lin, David H. Pan, Chieh-Min Cheng, David E. Holden, Adam Bush
  • Spacer layer for electrophoretic display device
    Publication number: 20030132925
    Abstract: An electrophoretic display device includes a spacer layer sandwiched between two conductive film substrates, the spacer layer defining a multiplicity of individual reservoirs within the display device which are filled with a display liquid.
    Type: Application
    Filed: January 16, 2002
    Publication date: July 17, 2003
    Inventors: Pinyen Lin, David H. Pan, Chieh-Min Cheng, David E. Holden, Adam Bush
  • Method of making a thin film transistor structure with improved source/drain contacts
    Patent number: 5362660
    Abstract: Minimum line spacing is reduced and line spacing uniformity is increased in thin film transistors by employing source/drain metallization having a first relatively thin layer of a first conductor and a second relatively thick layer of a second conductor. The second conductor is selected to be one which may be preferentially etched in the presence of the first conductor whereby the first conductor acts as an etch stop for the etchant used to pattern the second conductor portion of the source/drain metallization. This etching is preferably done using dry etching. Dry etching typically provides substantially better control of line width than wet etching. The etching of the second conductor can be done with a dry etch process which etches the photoresist at substantially the same rate as the second conductor whereby the second conductor is provided with a sidewall slope of substantially 45.degree. which improves the quality of passivation provided by subsequent deposition of a conformal passivating layer.
    Type: Grant
    Filed: November 18, 1992
    Date of Patent: November 8, 1994
    Assignee: General Electric Company
    Inventors: Robert F. Kwasnick, George E. Possin, David E. Holden, Richard J. Saia
  • Thin film transistor structure with improved source/drain contacts
    Patent number: 5198694
    Abstract: Minimum line spacing is reduced and line spacing uniformity is increased in thin film transistors by employing source/drain metallization having a first relatively thin layer of a first conductor and a second relatively thick layer of a second conductor. The second conductor is selected to be one which may be preferentially etched in the presence of the first conductor whereby the first conductor acts as an etch stop for the etchant used to pattern the second conductor portion of the source/drain metallization. This etching is preferably done using dry etching. Dry etching typically provides substantially better control of line width than wet etching. The etching of the second conductor can be done with a dry etch process which etches the photoresist at substantially the same rate as the second conductor whereby the second conductor is provided with a sidewall slope of substantially 45.degree. which improves the quality of passivation provided by subsequent deposition of a conformal passivating layer.
    Type: Grant
    Filed: January 24, 1992
    Date of Patent: March 30, 1993
    Assignee: General Electric Company
    Inventors: Robert F. Kwasnick, George E. Possin, David E. Holden, Richard J. Saia