Abstract: A FIFO is implemented as a buffer to encrypt/decrypt packet data and return the data to the same location where it was initially stored. No additional buffer or difficult buffer size decision is therefore required to compensate for the latency associated with the encryption/decryption. The FIFO implementation includes primary and secondary pointers. The primary pointers are available to the transmit/receive circuitry and the secondary pointers are used by the cryptographic circuit. When data is initially loaded into the FIFO, the FIFO does not report data availability to the primary user until the secondary user (cryptographic service) has read a block and returned the block to the same location. The FIFO is implemented via a single port RAM. Blocks are based on the encryption block size. The FIFO similarly reports packet availability based on application packet sizes (such as 188 MPEG2 transport stream packets).

Abstract: An IEEE 1394 serial bus, during bus initialization, transmits a plurality of self-ID packets across the bus. Each node on the bus is operable to receive the self-ID packet from the bus (140) via receiver (146). Asynchronous packets and isochronous packets are stored in a FIFO (166) for later use by a host interface (150). The self-ID packets are verified by a hardware circuit (170) that provides verification of the self-ID packets as they are received without requiring the software to later evaluate the self-ID packets from storage in the FIFO (166). If an error is determined, this is stored in registers (164) for later processing by the host interface (150).