Abstract: An efficient leading zero/leading one anticipator (LZA) that can operate in parallel with a floating point adder is disclosed. In one embodiment, the LZA can be implemented in three levels of N-NARY logic, wherein the first logic level generates dit-level propagate-generate-zero (PGZ) patterns and carry out signals from the input dits of the adder operands. The second logic level produces a find-zero and a find-one output signal for each two-dit group of the adder result by combining PGZ patterns for the two dits within the group with the carry-out signal from the dit immediately preceding the two-dit group. The third logic level combines find-zero and find-one output signals for each two-dit group to produce find-one and find-zero coarse and medium shift select signals.