Abstract: A scaffold system includes at least two essentially vertical support assemblies having an upper end and a lower end, wherein each essentially vertical support assembly includes at least two vertical support members connected by at least one horizontal member. A platform is attached proximate to the upper ends of the at least two essentially vertical support assemblies, wherein the vertical support assemblies are positioned to be proximate to a structure. One or more gap fillers are movably attached adjacent to the platform along at least a portion of the platform length and are configured to extend at least a portion of the platform towards the structure. One or more movable gates are attached to the essentially vertical support assemblies of one or more movable scaffolds, wherein the movable scaffolds are configured to be positioned on opposite sides of the structure to enable access to a top of the structure, and the movable gates may be connected to each other over the top of the structure.

Abstract: A logic circuit for testing the reliability of an ASIC includes an array circuit having a plurality of matrix arrays each having a plurality of inputs. The plurality of matrix arrays being positioned in a predetermined row and column of the array circuit and being responsive to a plurality of input signals applied thereto for providing a respective row and column output. A parity circuit responsive to the row and column outputs of the plurality of matrix arrays for causing an output signal at an output of the logic circuit to be in a first logic state whenever the row outputs of the plurality of matrix arrays are logically different, or whenever the column outputs of the plurality of matrix arrays are logically different. A stimulus circuit coupled to the plurality of inputs of the plurality of matrix arrays for supplying the plurality of input signals to exhaustively stimulate each one of the plurality of matrix arrays with all possible logic combinations.

Abstract: A design and method of exhaustively verifying the boolean functionality of both combinational and sequential cells for Application Specific Integrted Circuit gate array and standard cell libraries is provided. A single integrated circuit includes a plurality of cells or macros from the library. A Gray code generator provides a plurality of Gray code signals to the cells in response to a binary counter. The binary and Gray code signals stimulate each state of each cell. A multiplexed output indicates the functionality of each state.

Abstract: A bidirectional switching circuit is provided for testing a large number of AC data paths of LSI macrocell arrays. The circuit includes a plurality of bidirectional pins, a first logic means, and a second logic means. The switching circuit may be used to deskew a general purpose LSI tester wherein any pin may be used for input or output and the pulse at any pin may be inverted. The second logic means, receiving signals on selected pins, initializes the first logic means thereby determining which pins may be used for testing the data path desired.