Abstract: A 3-D LADAR imaging system incorporating stacked microelectronic layers is provided. A light source is imaged upon a target through beam shaping optics. Photons reflected from the target are collected and imaged upon a detector array though collection optics. The detector array signals are fed into a multilayer processing module wherein each layer includes detector signal processing circuitry. The detector array signals are amplified, compared to a user-defined threshold, digitized and fed into a high speed FIFO range bin. Dependant on the value of the digit contained in the bins in the register, and the digit's bin location, the time of a photon reflection from a target surface can be determined. A T0 trigger signal defines the reflection time represented by each bin location by resetting appropriate circuitry to begin processing.

Abstract: A 3-D LADAR imaging system incorporating stacked microelectronic layers is provided. A light source is imaged upon a target through beam shaping optics. Photons reflected from the target are collected and imaged upon a detector array though collection optics. The detector array signals are fed into a multilayer processing module wherein each layer includes detector signal processing circuitry. The detector array signals are amplified, compared to a user-defined threshold, digitized and fed into a high speed FIFO range bin. Dependant on the value of the digit contained in the bins in the register, and the digit's bin location, the time of a photon reflection from a target surface can be determined. A T0 trigger signal defines the reflection time represented by each bin location by resetting appropriate circuitry to begin processing.

Abstract: An electronic package is disclosed in which a plurality of stacked "same function" IC chips are designed to be used in lieu of a single IC chip, and to fit into a host computer system, in such a way that the system is "unaware" that substitution has been made. Memory packages are of primary interest, but other packages are also feasible, such as packages of FPGA chips. In order to "translate" signals between the host system and the stacked IC chips, it is necessary to include suitable interface circuitry between the host system and the stacked chips. Specific examples are disclosed of a 4 MEG SRAM package containing 4 stacked IC chips each supplying a 1 MEG memory, and of 64 MEG DRAM packages containing 4 stacked IC chips each supplying a 16 MEG memory. The interface circuitry can be provided by a single special purpose IC chip included in the stack, referred to as a VIC chip, which chip provides both buffering and decoding circuitry. Additionally, the VIC chip should provide power supply buffering.