Abstract: A method can include executing a store instruction that instructs storing of data at an address and, in response to the store instruction, inserting a preloading instruction after the store instruction but before a dependent load instruction to the address. Executing the store instruction can include invalidating a data entry of a cache array at an address of the cache array corresponding to the address and writing the data to a backing memory at an address of the backing memory corresponding to the address. The preloading instruction can cause filling the data entry of the cache array, at the address of the cache array corresponding to the address, with the data from the backing memory at the address of the backing memory corresponding to the address and validating the data entry of the cache array.

Abstract: A system and method of tracking multiple non-identification tagged requests in a system with multiple responders are disclosed. In one embodiment, an electronic memory system comprises a memory configured to implement a plurality of response queues, wherein one response queue is associated with one responder from a plurality of responders, and wherein a responder is a device capable of resolving the memory request. A tracking module is configured to assign identification information to a memory request that is received and store the identification information in one or more queues of the plurality of response queues; and to transmit the memory request to each responder that is associated with the one or more queues. A response module is configured to associate the identification information in the one or more queues with a response upon receiving the response from the one or more responders.

Abstract: Devices, systems, methods, and other embodiments associated with a cache memory are described. In one embodiment, a cache tag array includes tag banks. The cache memory further includes a bank selector configured to receive an address and to apply a hash function that maps the address to one of the tag banks.

Abstract: A programmable cache and cache access protocol that can be dynamically optimized with respect to either power consumption or performance based on a monitored performance of the cache. A monitoring unit monitors cache misses, load use penalty, and/or other performance parameter, and compares the monitored values against a set of one or more predetermined thresholds. Based on the comparison results, a cache controller configures the programmable cache to operate in a parallel mode, to increase cache performance at the cost of greater power consumption, or in a serial mode, to conserve power at the cost of unnecessary performance. A banked cache memory that supports aligned and unaligned instruction fetches using a banked access strategy, and a cache access controller that includes a prefetch capability are also described.

Abstract: A system and method of tracking multiple non-identification tagged requests in a system with multiple responders using one or more tracking queues. In some embodiments, the system and method may be implemented in a snoop filter covering multiple caches. In some embodiments, a data-less bus query may be used to update the status of a requested line.

Abstract: Set-associative caches having corresponding methods and computer programs comprise: a data cache to provide a plurality of cache lines based on a set index of a virtual address, wherein each of the cache lines corresponds to one of a plurality of ways of the set-associative cache; a translation lookaside buffer to provide one of a plurality of way selections based on the set index of the virtual address and a virtual tag of the virtual address, wherein each of the way selections corresponds to one of the ways of the set-associative cache; and a way multiplexer to select one of the cache lines provided by the data cache based on the one of the plurality of way selections.

Abstract: Non-processor agents, such as bus agents, may directly access processor caches. A coherency protocol ensures that cache coherency is maintained.

Abstract: A programmable cache and cache access protocol that can be dynamically optimized with respect to either power consumption or performance based on a monitored performance of the cache. A monitoring unit monitors cache misses, load use penalty, and/or other performance parameter, and compares the monitored values against a set of one or more predetermined thresholds. Based on the comparison results, a cache controller configures the programmable cache to operate in a parallel mode, to increase cache performance at the cost of greater power consumption, or in a serial mode, to conserve power at the cost of unnecessary performance. A banked cache memory that supports aligned and unaligned instruction fetches using a banked access strategy, and a cache access controller that includes a prefetch capability are also described.

Abstract: A system and method of tracking multiple non-identification tagged requests in a system with multiple responders using one or more tracking queues. In some embodiments, the system and method may be implemented in a snoop filter covering multiple caches. In some embodiments, a data-less bus query may be used to update the status of a requested line.

Abstract: A processor includes a first level of cache memory and a first set of instructions configured to implement a first cache coherency protocol. The processor also includes a second set of instructions configured to implement a second cache coherency protocol and a cache coherency protocol selector having at least two choice-states. The processor further includes a cache coherency implementer configured to implement the first cache coherency protocol or the second cache coherency with respect to the first level of cache memory based on a selected choice-state of the cache coherency protocol selector.

Abstract: A semiconductor chip is described having a plurality of processing cores. The semiconductor chip also includes a plurality of test controllers. Each test controller is associated with a different one of the processing cores. The semiconductor chip also includes a test port having a first serial input and a first serial output. The first serial input is to receive serial test input data provided to the semiconductor chip. The first serial output is to provide serial output data provided by the semiconductor chip. The semiconductor chip further includes switch circuitry coupled to the test port and the plurality of test controllers. The switch circuitry is to route the serial test input data to one of the plurality of test controllers and to route the serial output data from one of the plurality of test controllers to the first serial output. The semiconductor chip further includes a configuration register coupled to the switch circuitry to establish the switch circuitry's routing configuration.

Abstract: A method and apparatus for power optimized replay. In one embodiment, the method includes the issuance of an instruction selected from a queue. Once issued, the instruction may be enqueued within a recirculation queue if completion of the instruction is blocked by a detected blocking condition. Once enqueued, instructions contained within the recirculation queue may be reissued once a blocking condition of an instruction within the recirculation queue is satisfied. Accordingly, a power optimized replay scheme as described herein optimizes power while retaining the advantages provided by selectively replaying of blocked instructions to improve power efficiency.

Abstract: A bus control system includes N bus agents each having a corresponding bus request delay and M bus agents each having a corresponding bus request delay. A controller determines the bus request delays of the N bus agents and the M bus agents and grants concurrent ownership of a bus to each of the N bus agents and non-concurrent ownership of the bus to each of the M bus agents based on the determination. M and N are integers greater than 1.

Abstract: A method and apparatus for optimizing line writes in cache coherent systems. A new cache line may be allocated without loading data to fill the new cache line when a store buffer coalesces enough stores to fill the cache line. Data may be loaded to fill the line if an insufficient number of stores are coalesced to fill the entire cache line. The cache line may be allocated by initiating a read and invalidate request and asserting a back-off signal to cancel the read if there is an indication that the coalesced stores will fill the cache line.

Abstract: A method and apparatus for power optimized replay. In one embodiment, the method includes the issuance of an instruction selected from a queue. Once issued, the instruction may be enqueued within a recirculation queue if completion of the instruction is blocked by a detected blocking condition. Once enqueued, instructions contained within the recirculation queue may be reissued once a blocking condition of an instruction within the recirculation queue is satisfied. Accordingly, a power optimized replay scheme as described herein optimizes power while retaining the advantages provided by selectively replaying of blocked instructions to improve power efficiency.

Abstract: A system, method, and apparatus for a cache memory to support a low power mode of operation.

Abstract: Briefly, descriptions of embodiments in accordance with the invention, a test access port for a multi-core processor.

Abstract: Some embodiments of the invention include an address interconnect and a data interconnect to transfer data among a number of devices. The data interconnect is configured to transfer data among the devices via multiple transfer paths. A transfer of data on one transfer path is independent from a transfer of data on another transfer path. In some cases, data is concurrently transferred among more than two of the devices on at least one of the address interconnect and the data interconnect. Other embodiments are described and claimed.

Abstract: Systems and methods for early fixed latency subtractive decoding are disclosed. The subtractive decoding device speculatively acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bus transaction may therefore be accomplished each new time period. A bus transaction may be retried if no acknowledgement occurs within the fixed time period.

Abstract: A method, apparatus, and system are provided for testing multi-core processors. The testing includes a test control mechanism and a multi-core processor including a set of cores with at least one core having a test access port controller (TAPC), distributed data, and a set of distributed control registers. The multi-core processor and the test control mechanism further having a configuration to provide testing the multi-core processor. The test control mechanism is modified to simultaneously test multiple cores.