Patents by Inventor David E. Moran

David E. Moran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240066329
    Abstract: A method and system for closed-circuit combined unit respiration, is disclosed. More specifically, an enriched air, multi-use closed-circuit self-contained breathing apparatus for on-demand transition between a powered air purifying respirator (PAPR) mode and a closed-circuit rebreather mode, is disclosed. The system may comprise a carbon dioxide scrubbing canister configured to receive an exhaled gas and scrub carbon dioxide from the exhaled gas when in a closed-circuit mode. A breathing bag may receive the scrubbed gas when in the closed-circuit mode. The scrubbed gas may be infused with oxygen, resulting in an enriched gas when in the closed-circuit mode. A cooler comprising a plurality of heatsink fins may cool the enriched gas and a breathing hose may transmit the enriched gas for inhalation when in the closed-circuit mode. The system may further comprise a PAPR to intake and filter external air for inhalation when in the PAPR mode.
    Type: Application
    Filed: December 20, 2021
    Publication date: February 29, 2024
    Applicant: Mine Survival, Inc.
    Inventors: Robert N. Moran, Francisco Elias Hernandez, David E. Cowgill
  • Patent number: 7315305
    Abstract: A system and method for visualizing data. Data are provided either in the form of data values of a data array or in the form of a geometric representation. A data array may be, for example, a sparse matrix. A geometric representation, may be, for example, an integrated circuit layout coded in a geometric description language. Data provided in the form of data values are associated with geometric shapes placed on a grid. Information placed on the grid is then reported to a user. If data are provided in the form of a geometric representation, then data values are extracted from the geometric representation. A graphic representation is generated from the extracted data values. The graphic representation is exhibited to a user.
    Type: Grant
    Filed: January 4, 1999
    Date of Patent: January 1, 2008
    Assignee: International Business Machines Corporation
    Inventors: Cassondra L. Crotty, Daria R. Dooling, David E. Moran, Ralph J. Williams
  • Patent number: 6788302
    Abstract: The present invention divides a large graphics file into smaller “frames” of graphics files. The division process is preferably load balanced amongst any number of processors. This allows many processors to be used in parallel to divide the large graphics file and to then process the smaller output frames. Additionally, the load balancing is performed in such a manner that only portions of the graphics file need be loaded by any one processor. This saves memory and computational requirements. Preferably, the graphics file is divided in a three-dimensional manner, such that any one processor will be assigned one three-dimensional block or volume of the graphics file. The three-dimensional partition of the graphics file will become one frame, and the one processor accesses the graphics file to copy its three-dimensional partition into the new output frame.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: September 7, 2004
    Assignee: International Business Machines Corporation
    Inventors: Gary S. Ditlow, Daria R. Dooling, David E. Moran, Ralph J. Williams
  • Patent number: 6601025
    Abstract: A method is provided for designing an integrated circuit that includes receiving a graphical description of the integrated circuit, extracting shapes relating to a specific circuit function from the graphical description of the integrated circuit, and partitioning the extracted shapes into a plurality of segments. The method may form an electrical representation of the integrated circuit for each of the plurality of segments and solve a matrix equation (Gv=i) for each of the plurality of segments based on the electrical representation.
    Type: Grant
    Filed: August 10, 1999
    Date of Patent: July 29, 2003
    Assignee: International Business Machines Corporation
    Inventors: Gary S. Ditlow, Daria R. Dooling, Richard L. Moore, David E. Moran, Thomas W. Wilkins, Ralph J. Williams
  • Publication number: 20020050995
    Abstract: A system and method for visualizing data. Data are provided either in the form of data values of a data array or in the form of a geometric representation. A data array may be, for example, a sparse matrix. A geometric representation, may be, for example, an integrated circuit layout coded in a geometric description language. Data provided in the form of data values are associated with geometric shapes placed on a grid. Information placed on the grid is then reported to a user. If data are provided in the form of a geometric representation, then data values are extracted from the geometric representation. A graphic representation is generated from the extracted data values. The graphic representation is exhibited to a user.
    Type: Application
    Filed: January 4, 1999
    Publication date: May 2, 2002
    Inventors: CASSONDRA L. CROTTY, DARIA R. DOOLING, DAVID E. MORAN, RALPH J. WILLIAMS
  • Patent number: 6301690
    Abstract: A method for manufacturing an integrated circuit having improved defect-limited yield. Each conductor on the integrated circuit is represented as an electrical element of a network, having branch voltages and currents. The width of the conductor is advantageously selected to have the minimum width necessary to produce signal levels that have sufficient noise margins. An integrated circuit conductive grid is thus realized having a reduced cross sectional area along a portion of various conductor element lengths, to reduce the risk that particles produced during manufacturing will result in bridging of adjacent conductor elements.
    Type: Grant
    Filed: July 12, 1999
    Date of Patent: October 9, 2001
    Assignee: International Business Machines Corporation
    Inventors: Gary S. Ditlow, Daria R. Dooling, David E. Moran, Richard L. Moore, Gustavo E. Tellez, Ralph J. Williams, Thomas W. Wilkins
  • Patent number: 5634001
    Abstract: A method and system are provided for determining a guard band voltage differential for testing a microprocessor. The guard band voltage differential approximates microprocessor circuit propagation delay degradation expected to occur over the life of the microprocessor. The system and method are performed by first partitioning a microprocessor into a plurality of cones of n circuit level models. Timing simulation data and degradation data are created to represent, respectively, the timing operation for each of the circuit level model circuit paths, and the hot-electron effects on propagation delay degradation for each of the circuit level models. Propagation delay is identified using this data for each of the circuit paths for the circuit level models at times corresponding to the beginning-of-life and end-of-life of the microprocessor. Propagation delay degradation is calculated as the difference between the propagation delay at these times.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: May 27, 1997
    Assignee: International Business Machines Corporation
    Inventors: Steven W. Mittl, David E. Moran, Timothy J. O'Gorman, Kimball M. Watson
  • Patent number: 5533197
    Abstract: A method of assessing the tolerance of a microprocessor to propagation time degradation caused by electromigration effects and hot electron effects is provided. Reference values for interconnection resistance (IR) degradation and drain current (DC) degradation are compute, at nominal fabrication process and microprocessor lifetime application conditions. These results may be tabulated for a plurality of output driver load capacitances. Test IR degradation and test DC degradation values are calculated by scaling the reference IR and DC degradation values, respectively, for actual test conditions. The circuit propagation time and the propagation delay degradation caused by both electromigration and hot electron effects are calculated at process and lifetime environmental conditions.
    Type: Grant
    Filed: October 21, 1994
    Date of Patent: July 2, 1996
    Assignee: International Business Machines Corporation
    Inventors: David E. Moran, Timothy J. O'Gorman, Kimball M. Watson