Abstract: Techniques are provided for sparse array RF imaging for surveillance applications. Objects in a three dimensional (3-D) image-data-set obtained from multi-static radio frequency detection data are classified, for example, as human or non-human. One or more geometric image features are extracted from the image-data-set that support a target classification process; and the one or more objects are classified as a threat based on a parametric evaluation of the extracted geometric image features.

Abstract: Techniques are provided for sparse array RF imaging for surveillance applications. The present invention enables object image identification using a sparsely populated array of distributed radio nodes deployed and operated as a radar detection, tracking and identification application. Three-dimensional object images are formed, from which estimates of extent and shape can be extracted for objects that are detected in the vicinity of the deployed radar array. In addition, techniques are provided for the identification and/or classification of vehicles, humans and fauna through feature extraction from the formed three-dimensional images.

Abstract: Techniques are provided for sparse array RF imaging for surveillance applications. The present invention enables object image identification using a sparsely populated array of distributed radio nodes deployed and operated as a radar detection, tracking and identification application. Three-dimensional object images are formed, from which estimates of extent and shape can be extracted for objects that are detected in the vicinity of the deployed radar array. In addition, techniques are provided for the identification and/or classification of vehicles, humans and fauna through feature extraction from the formed three-dimensional images.

Abstract: A register array accessible by both a system microprocessor and a digital signal processor of a PC audio circuit, comprising: (i) a random access memory (RAM) having a first port connected to a digital signal processor input/output port, and a second port connected to a RAM input/output port; (ii) a register data port connected to the RAM input/output port and having a connection to a register data bus; (iii) timing circuitry for timing the register array operations; (iv) row and column select circuitry for respectively selecting rows and columns in said RAM; and (v) an input/output channel ready signal line connected to said timing circuitry. The RAM includes a plurality of edge bits each of which stores a value indicating whether processing of a row of data values stored in said RAM is active or inactive. The system microprocessor is disabled from accessing the RAM whenever the RAM is not idle or the microprocessor seeks to access a row of the RAM currently subject to access by the digital signal processor.

Abstract: A clock switcher circuit for providing at least one set of clock signals selected from a plurality of clock sources. A first clock signal having a first pulse length and a second clock signal having a second pulse length are circuit inputs. Another circuit input is a clock selection input. When the clock selection input indicates a new output clock signal, different from the then current output clock signal, should be output by the circuit, the circuit provides a means for switching to output the new output clock signal. In switching to output the new output clock signal, the circuit prevents the occurrence of the output clock signal ever having a pulse shorter than the normal pulse length of the then current output clock signal, whether the then current output clock signal is the first clock signal or the second clock signal.