Abstract: A system comprises a sensor device and processing circuitry. The sensor device comprises a housing configured to be disposed above shoulders of a patient, a plurality of electrodes on the housing, a motion sensor, and sensing circuitry configured to sense a brain electrical signal and a cardiac electrical signal via the electrodes, and a motion signal via the motion sensor. The processing circuitry is configured to determine values over time of one or more parameters from the brain electrical signal, determine values over time of one or more parameters from the cardiac electrical signal, and generate at least one of a detection, prediction, or a classification a condition of the patient based on the values and the motion signal.

Abstract: A package for a medical device such as an intermittent catheter has a case and a cap connected by threads. The case includes a hollow tube which is closed at one end and open at the other. A shoulder is formed near one end of the case. Above the shoulder is a cylindrical ferrule that includes external threads. The cap has internal threads selectably engageable with the threads on the ferrule to form a liquid-tight seal between the cap and case when the cap is installed on the case.

Abstract: A low cost, low phase noise microwave synthesizer includes a DDS modulation circuit and a phase-locked loop. The DDS modulation circuit modulates the output of a DDS to a high frequency. The phase-locked loop downconverts the DDS output and locks the downconverted signal to a relatively low frequency, fixed reference.

Abstract: A low cost, low phase noise microwave synthesizer includes a DDS modulation circuit and a phase-locked loop. The DDS modulation circuit modulates the output of a DDS to a high frequency. The phase-locked loop downconverts the DDS output and locks the downconverted signal to a relatively low frequency, fixed reference.

Abstract: A timing circuit for ATE generates an output clock from an input clock and controls output pulse width. The timing circuit includes a differential driver having an input that receives the input clock, and having inverting and non-inverting outputs. The inverting output is coupled to a first phase-locked loop, and the non-inverting output is coupled to a second phase-locked loop. The first and second phase-locked loops respectively generate first and second clocks in response to respective rising and falling edges of the input clock. A combiner circuit converts the first and second clocks into narrow pulse trains, and the pulse trains respectively operate SET and RESET inputs of a SET/RESET flip-flop. The SET/RESET flip-flop generates an output clock having rising edges responsive to rising edges of the input clock, and falling edges responsive to falling edges of the input clock.