Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes formed in tiers. And, more particularly, to multiple, alternating silicon germanium (SiGe) and single crystalline silicon (Si) in different thicknesses to form tiers in which to form the horizontal access devices in vertical three-dimensional (3D) memory. The horizontally oriented access devices can have a first source/drain regions and a second source drain regions separated by single crystalline silicon (Si) channel regions. The single crystalline silicon (Si) channel regions can include a dielectric material to provide support structure to the single crystalline channel regions when forming the horizontal access devices in vertical three-dimensional (3D) memory. Horizontally oriented access lines can connect to gate structures opposing the channel regions. Vertical digit lines coupled to the first source/drain regions.

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source drain regions separated by silicon (Si) channel regions. A digit line having a global digit line (GDL) contact is formed in a trench adjacent to the first source/drain regions. In one example, the digit line is electrically isolated from a neighboring digit line at the bottom of the trench. In another example, the digit line is formed continuously along a bottom surface of trench to form shared digit lines between horizontal access devices, in two separate arrays, on opposing second vertical surfaces. The memory cells have horizontally oriented storage nodes coupled to the second source/drain regions and vertical digit lines coupled to the first source/drain regions.

Abstract: Methods and devices for a lateral three-dimensional memory device, are described herein. One method includes forming a thin film transistor including a first thermal process having a first range of temperatures, forming a capacitor bottom electrode of a capacitor structure including a second thermal process having a second range of temperature, wherein a maximum temperature in the second range of temperatures is less than a maximum temperature in the first range of temperatures, forming a CMOS structure including a third thermal process having a third range of temperatures, wherein a maximum temperature in the third range of temperatures is less than a maximum temperature in the second range of temperatures, and forming at least one other part of the capacitor structure.

Abstract: A drive line joint assembly (10) has splined driving and driven members (13,20), one of which has a protuberance (36) which extends axially along a spline (16,18) thereof to insure the absence of radial tolerance for balancing purposes. In a preferred form, a forged steel spline (16) has a resilient coating (40) bonded thereto, the coating preferably of a nylon or of other material having comparable low friction quality. The resilient protuberance is an integral part of the latter low friction coating and is formed by a broaching tool after the coating material has been applied to the spline. In a preferred embodiment, the protuberance extends only 0.001 to 0.003 inch above the surface of the coating, wherein the coating has a thickness in the range of 0.007 to 0.014 inch over the steel body portion of the spline. At least three of the protuberances are preferred, each circumferentially spaced from the other.