Patents by Inventor David E. Sweenor

David E. Sweenor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7558999
    Abstract: A system and method for diagnosing a failure in an electronic device. A disclosed system comprises: a defect table that associates previously studied features with known failures; and a fault isolation system that compares an inputted set of suspected faulty device features with the previously studied features listed in the defect table in order to identify causes of the failure.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: July 7, 2009
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, John M. Cohn, Leendert M. Huisman, Maroun Kassab, Leah M. Pfeifer Pastel, David E. Sweenor
  • Patent number: 7194706
    Abstract: A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: March 20, 2007
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, Greg Bazan, John M. Cohn, Matthew S. Grady, Leendert M. Huisman, Mark D. Jaffe, Phillip J. Nigh, Leah M. P. Pastel, Thomas G. Sopchak, David E. Sweenor, David P. Vallett
  • Patent number: 7089514
    Abstract: A method for defect diagnosis of semiconductor chip. The method comprises the steps of (a) identifying M design structures and N physical characteristics of the circuit design, wherein M and N are positive integers, wherein each design structure of the M design structures is testable as to pass or fail, and wherein each physical characteristic of the N physical characteristics is present in at least one design structure of the M design structures; (b) for each design structure of the M design structures of the circuit design, determining a fail rate and determining whether the fail rate is high or low; and (c) if every design structure of the M design structures in which a physical characteristic of the N physical characteristics is present has a high fail rate, then flagging the physical characteristic as being likely to contain at least a defect.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: August 8, 2006
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, Greg Bazan, John M. Cohn, Francis Gravel, Leendert M. Huisman, Phillip J. Nigh, Leah M. P. Pastel, Kenneth Rowe, Thomas G. Sopchak, David E. Sweenor