Abstract: A receiver has a first input port and a second input port both coupled to a differential amplifier through first and second input capacitors. A bias circuit coupled to the core side of the first input capacitor and to the core side of the second input capacitor is configured to provide a selected voltage to at least one of the first input and the second input of the differential amplifier. In one embodiment, a common mode bias circuit provides a common mode voltage to both inputs of a differential amplifier. In a particular embodiment, a run length detector monitors the output of the differential amplifier and provides a run length feedback signal or an average bit density feedback signal to the set the selected voltage between periods of data reception.

Abstract: A self-synchronizing system that provides a master system component and a master clock source to provide a stable timing reference to the master system component. Timing information is then propagated throughout the system via encoded transmissions containing the timing information, or conversely, propagated by request via a training sequence. All system components other than the master system component do not require a separate clock input, since frequency coherency is maintained by internal time bases that have been calibrated to the frequency of the propagated timing information.

Abstract: Methods and apparatus for configuring a programmable integrated circuit are described. In one example, a configuration stream having first data for programming first locations in a configuration memory and an instruction for referencing circuitry in the programmable integrated circuit is received. Second data is obtained from the circuitry based on the instruction. Second locations in the configuration memory are programmed in response to the second data.

Abstract: A device and a method for processing high data rate serial data includes a VCO initial frequency calibration circuit. The circuit includes a frequency detection block for indicating a difference between a reference clock and a divided VCO clock, a frequency calibration block that produces a digital output signal based upon the difference between the reference clock and the divided VCO clock, and a digital-to-analog converter for producing an analog VCO adjust signal. The frequency detection block produces a plurality of signals based upon the reference clock and the divided VCO clock. A plurality of user selected inputs selects a frequency detection lock range and hysteresis range and a coarse loop open calibration lock and hysteresis range. The frequency calibration block implements a state machine for producing the digital output signal that sets the initial operating frequency then adjusts the frequency of the VCO clock.

Abstract: A receiver has a first input port and a second input port both coupled to a differential amplifier through first and second input capacitors. A bias circuit coupled to the core side of the first input capacitor and to the core side of the second input capacitor is configured to provide a selected voltage to at least one of the first input and the second input of the differential amplifier. In one embodiment, a common mode bias circuit provides a common mode voltage to both inputs of a differential amplifier. In a particular embodiment, a run length detector monitors the output of the differential amplifier and provides a run length feedback signal or an average bit density feedback signal to the set the selected voltage between periods of data reception.

Abstract: A method and apparatus to allow dynamic port provisioning of communication ports within a Programmable Logic Device (PLD). The dynamic port provisioning combines configuration of serial Input/Output (I/O) devices with simultaneous reconfiguration of a portion of programmable logic resources within the PLD and processor functions to implement a particular communication protocol. The dynamic port provisioning is facilitated for a single channel, without affecting the dynamic port provisioning of other communication channels operating within the PLD.

Abstract: A communication system includes a transmitter, a communication channel, and a receiver. The transmitter includes a pre-emphasis module, a summing module, a line driver, and a decision feedback pre-emphasis (DFP) module to produce a pre-emphasized serial stream of data based on a communications channel response and an inter-symbol interference level. The receiver includes a linear equalizer, a summing module, a decision module, and a decision feedback equalization (DFE) module. The linear equalizer produces an equalized serial stream of data. The summing module sums at least one data element of the equalized serial stream of data with DFE data elements to produce equalized data elements. The decision module interprets the equalized data elements to produce interpreted data elements to DFE module, which produces the DFE data elements from the interpreted data elements.

Abstract: A receiver that includes: an oversampling module that converts a serial stream of data into a plurality of streams of oversampled data based on the receive clock; a transition location module that determines transition locations of the streams of oversampled data and the receive clock; a pointer adjust module that determines a pointer variable based on the transition locations and the receive clock; a data selection module that determines an equivalent data value for the streams of oversampled data based on the pointer variable; a staging register module that produces an offset data word and an extra data word from the equivalent data value for the oversampled data streams; and a output register module that produces a parallel data output from at least one of the offset data word and the extra data word.

Abstract: According to particular example embodiments, an integrated circuit includes one or more serializing data transmitters. Each such data transmitter is arranged to transmit data on a respective data output port of the integrated circuit, wherein the respective data output port for at least one of the data transmitters is dedicated to transmitting periodic data used for clocking a respective target circuit. In other particular embodiments involving feedback, phase-locked loop (PLL) signal control and/or delay-locked loop (DLL) signal control is achieved in functional blocks of a programmable logic device (PLD). The PLD is responsive to a source clock and includes a configurable logic array that includes configurable logic blocks and configurable routing blocks, and the respective data output port for at least one of the data transmitters provides a respective target clock.

Abstract: Circuitry for equalizing a high data rate serial data stream that receives low frequency and high frequency test tones, accurately measures an amount of attenuation experienced by the high frequency test tone in relation to the low frequency test tone, and accordingly, produces equalization data that results in a corresponding amount of equalization or pre-emphasis being added to an outgoing signal. More specifically, however, the present invention includes both open loop and closed loop systems for equalizing or adding pre-emphasis to a signal with attenuation. In the open loop transceiver system, a presumption is made that an amount of attenuation in both the outgoing and ingoing directions are equal. In the closed loop transceiver system, a receiver determines an amount of equalization and produces the equalization data to a remote transceiver.

Abstract: A method and apparatus to provide various mechanisms to improve yield of an integrated circuit (IC) employing serial input/output (I/O) communication devices. A single error correction model provides one spare transceiver per group of primary transceivers, whereby reconfiguration of the IC isolates the defective transceiver and configures the replacement transceiver for operation in its place. A multiple error correction model is also provided, whereby multiple replacement transceivers may be configured to replace multiple defective transceivers. The replacement mechanism may occur during various phases of the IC, such as during wafer testing, final testing, or post-deployment testing.

Abstract: A method and apparatus for providing clock phase alignment in a transceiver system are disclosed. Circuits are provided for providing clock phase alignment to adjust and align the phase between clock domain boundaries and for maintaining alignment of multiple outputs signals.

Abstract: A phase-locked loop with a non-integer divider utilizes a state machine to periodically select a new clock from a plurality of clocks for comparison to a reference signal after division by an integer divide by N block. Based on a desired divider ratio, the state machine selects the new clock that is phase shifted with respect to a presently selected clock. Each change from the presently selected clock to the new clock produces a selected clock cycle that is expanded or contracted by the amount of phase shift between the new clock and the presently selected clock. The integer divide by N block divides the selected clock by the integer portion of the desired divider ratio producing a divided clock that is effectively divided by a non-integer amount.

Abstract: An apparatus for and method of serially transmitting a message between first and second devices coupled to a data or clock line in a process control device is disclosed. A first transition of the data or clock signal is generated during a signal cycle. A second transition of the signal is generated during the first signal cycle in order to control the duty cycle of the signal during the first signal cycle. If the duty cycle of the signal during the first signal cycle has a first value, then the first signal cycle is representative of a first data state transmitted between the first and second devices. If the duty cycle of the signal during the first signal cycle has a second value, then the first signal cycle is representative of a second data state transmitted between the first and second devices.

Abstract: A field instrument includes an input circuit having a transistor bridge rectifier which is couplable to a power supply. The transistor bridge rectifier is configured to provide power from the power supply to a remainder of the field instrument.

Abstract: The present invention includes a process control instrument having an improved data bus protocol for facilitating communications between master and slave nodes. The process control instrument includes a microprocessor operating in accordance with the SPI data bus protocol, first and second peripheral devices, and a data bus coupled to the microprocessor and the first and second peripheral devices. The improved data bus protocol used in the process control instruments of the present invention provides numerous advantages such as reduced printed circuit board space requirements and greater interchangeability of peripheral and master node components.

Abstract: A transmitter for use in a process control setting includes a sensor adapted to couple to a process and provide a sensor output related to a parameter of the process. A modulator coupled to the sensor output responsively provides a digital bit stream output representative of the sensor output. A filter provides a current decimation output. A comparator compares a previous decimation output with the current decimation output. Circuitry is provided for transmitting an output related to the parameter based upon the current decimation.

Abstract: A bit serial decoder is disclosed decoding an encoded non-return to zero (NRZ) signal without the use of external clock. Transitions within the encoded NRZ signal cause a differential voltage signal to be output. This differential voltage increases at a constant rate between two transitions. At the second transition the magnitude of the differential voltage is compared to a preset value to determine a number of consecutive like bits. These consecutive bits can then be transmitted in one step to a storage means.

Abstract: A calibrating system calibrates an analog-to-digital converter which has an integrator and first and second reference current sources. A quantity of charge is accumulated in the integrator. The quantity of charge is removed from the integrator by applying the first and second reference currents to the integrator for first and second time periods until the accumulated charge reaches a threshold level. The quantity of charge is reaccumulated in the integrator and again removed by applying the first and second reference currents for third and fourth time periods wherein the first and second time periods are different from the third and fourth time periods. The relative magnitude of the first and second reference currents is determined based on the first, second, third and fourth time periods.

Abstract: A method and apparatus for decoding a specially encoded bit stream without the use of an external clock. A bit stream is encoded so that the relative lengths of the pulse widths between the transitions in the bit stream are indicative of the type bit being transmitted. A decoder receives the bit stream, measures the lengths of the pulses between the transitions, determines the type of bit by comparing the lengths, and stores the bit in a shift register. The bits can then be output in parallel form.