Abstract: A data processing system is comprised of: a system bus having a main memory coupled thereto; multiple high level cache memories, each of which has a first port coupled to said system bus and a second port coupled to a respective processor bus; and each processor bus being coupled through respective low level cache memories to respective digital computers. In the high level cache memories, data words are stored with respective tag bits which identify each data word as being stored in one of only four states which are shared, modified, invalid, or exclusive. In the low level cache memories, data words are stored with respective tag bits which identify each data word as being stored in only one of three states which are shared, modified or invalid.

Abstract: A pulse synchronizing module includes: a) a pair of input leads which respectively receive a clock signal and digital input pulses that are asynchronous to the clock signal; b) a first counter circuit which is triggered by rising edge transitions in the input pulses, and a second counter circuit which is triggered by falling edge transitions in the input pulses; c) first and second registers which, in synchronization with the clock signal, sample respective counts in the first and second counter circuits; and d) an output circuit, coupled to the first and second registers. This output circuit generates, the rising edge of an output pulse, in synchronization with the clock signal, when the count sample in the first register differs from the number of rising edges which the output circuit previously generated; and it generates the falling edge of the output pulse, in synchronization with the clock signal, when the count sample in the second register differs from the number of falling edges previously generated.

Abstract: A multi-level distributed data processing system includes: 1) a system bus having a main memory coupled thereto; 2) multiple high level cache memories, each of which has a first port coupled to the system bus and a second port coupled to a respective processor bus; and, 3) each processor bus is coupled to multiple digital computers through respective low level cache memories. Further, each low level cache memory stores data words with respective tag bits which identify each data word as being shared, modified or invalid but never exclusive; and, each high level cache memory stores data words with respective tag bits which identify each data word as being shared, modified, invalid, or exclusive.

Abstract: A cache memory includes: a plurality of tag memory blocks, each of which stores multiple compare addresses; a first bus which sends a low order address to all of the tag memory blocks; a respective output from each tag memory block on which a compare address is read in response to the low order address; a second bus which carries a high order address; and, a comparator circuit which generates a miss signal when the compare address on the output from every tag memory block miscompares with the high order address. Each tag memory block further stores respective control bits with each compare address; and each tag memory block responds to the low order address by reading the compare address and the respective control bits, in parallel, on its respective output.