Abstract: A distributed system that manages resources of the distributed system without the need for complex time synchronization systems is described. The distributed system includes a resource manager that manages the resources of the distributed system. The resource manager assigns leases and renews leases of resources of the distributed system to clients in the distributed system. The leases specify the duration of time that the lease is awarded to clients.

Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

Abstract: A brake disc for a high performance vehicle comprises a rotor 20 formed of grey cast iron and comprising a friction ring 24 annular about an axis of rotation 26 and, coaxial with the friction ring 24, a tubular flange 28 extending axially from the friction ring 24 to a free end 28a and having a wall 28e with a radially inner face 28c and a radially outer face 28d. A hub 22 formed of aluminum is cast over the flange 28 to encapsulate at least a portion of the wall 28e, with which it has a shrink-fit connection. The encapsulated portion of the wall is made smooth (or otherwise formed with a varying radial dimension, or a screw thread) so as to permit differential thermal contraction, in an axial direction, of the hub 22 relative to the flange 28 as the hub 22 solidifies and cools after its casting. By this means, retained stresses in the hub 22 are minimized.

Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

Abstract: A distributed system that manages resources of the distributed system without the need for complex time synchronization systems is described. The distributed system includes a resource manager that manages the resources of the distributed system. The resource manager assigns leases and renews leases of resources of the distributed system to clients in the distributed system. The leases specify the duration of time that the lease is awarded to clients.

Abstract: A distributed system that manages resources of the distributed system without the need for complex time synchronization systems is described. The distributed system includes a resource manager that manages the resources of the distributed system. The resource manager assigns leases and renews leases of resources of the distributed system to clients in the distributed system. The leases specify the duration of time that the lease is awarded to clients.

Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

Abstract: A brake disc for a high performance vehicle comprises a rotor 20 formed of grey cast iron and comprising a friction ring 24 annular about an axis of rotation 26 and, coaxial with the friction ring 24, a tubular flange 28 extending axially from the friction ring 24 to a free end 28a and having a wall 28e with a radially inner face 28c and a radially outer face 28d. A hub 22 formed of aluminium is cast over the flange 28 to encapsulate at least a portion of the wall 28e, with which it has a shrink-fit connection. The encapsulated portion of the wall is made smooth (or otherwise formed with a varying radial dimension, or a screw thread) so as to permit differential thermal contraction, in an axial direction, of the hub 22 relative to the flange 28 as the hub 22 solidifies and cools after its casting. By this means, retained stresses in the hub 22 are minimised.

Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

Abstract: A brake disc (401) for a vehicle is shown. The brake disc has a hub (403) to be secured to a wheel or an axle of a vehicle, such that it will rotate about an axis (B). The brake disc also has a brake member (402) comprising an annular friction ring (501) having an inner radius (503) and an outer radius (504), and an axially extending hollow cylindrical flange (502) having an inner surface and an outer surface. The hub is a casting which extends over both the inner surface and the outer surface of the flange. The hub is formed of a first material and the friction ring is formed of a second material, and the first material has a lower density, a lower melting point, and a higher coefficient of linear thermal expansion than the second material.

Abstract: Apparatus and methods provide associative mapping of the blocks of two or more memory arrays such that data, such as pages of data, from the good blocks of the two or more memory arrays can be read in an alternating manner for speed or can be read in parallel for providing data to relatively wide data channels. This obviates the need for processor intervention to access data and can increase the throughput of data by providing, where configured, the ability to alternate reading of data from two or more arrays. For example, while one array is loading data to a cache, the memory device can be providing data that has already been loaded to the cache.

Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

Abstract: Non-volatile memory devices and methods of their operation are provided. One such non-volatile memory device has an interface and a control circuit. The non-volatile memory device is adapted to identify itself as a boot memory in response to receiving an interrogation request on the interface.

Abstract: Apparatus and methods provide associative mapping of the blocks of two or more memory arrays such that data, such as pages of data, from the good blocks of the two or more memory arrays can be read in an alternating manner for speed or can be read in parallel for providing data to relatively wide data channels. This obviates the need for processor intervention to access data and can increase the throughput of data by providing, where configured, the ability to alternate reading of data from two or more arrays. For example, while one array is loading data to a cache, the memory device can be providing data that has already been loaded to the cache.

Abstract: There is provided a method and apparatus for bus negotiation. One such method includes determining a configuration of a first bond pad, the first bond pad indicating whether a host is configured to communicate with a fixed data storage device or a removable data storage device. If the first bond pad indicates the host is configured to communicate with a fixed data storage device, then the method additionally includes determining the configuration of a second bond pad. The second bond pad indicates the supported bus width of the fixed data storage device.

Abstract: In an example, a single damascene structure is formed by, for example, providing a dielectric layer, forming a void in the dielectric layer, and forming a portion of a first two-terminal resistive memory cell and a portion of a second two-terminal resistive memory cell within the void. The portions of the two-terminal resistive memory cells may be vertically stacked within the void.

Abstract: In an example, a single damascene structure is formed by, for example, providing a dielectric layer, forming a void in the dielectric layer, and forming a portion of a first two-terminal resistive memory cell and a portion of a second two-terminal resistive memory cell within the void. The portions of the two-terminal resistive memory cells may be vertically stacked within the void.

Abstract: Split data error correction code (ECC) circuits including a control circuit coupled to an error correction code (ECC) circuit. The ECC circuit is adapted to generate at least one ECC code from user data of a first physical sector during a data access. The split data ECC circuit is adapted to write the at least one ECC code to a second physical sector if the data access is a write access and to compare the at least one generated ECC code with at least one ECC code stored in a second physical sector if the data access is a read access.

Abstract: Non-volatile memory devices and methods of their operation are provided. One such non-volatile memory device has an interface and a control circuit. The non-volatile memory device is adapted to identify itself as a boot memory in response to receiving an interrogation request on the interface.

Abstract: Data move operations in a memory device are described that enable identification of data errors. Error detection circuitry in the memory device can be operated using parity data or ECC data stored in the memory. Results of the error detection can be accessed by a memory controller for data repair operations by the controller.