Patents by Inventor David Entrikin

David Entrikin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10560114
    Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: February 11, 2020
    Assignee: Avnera Corporation
    Inventors: Jianping Wen, Ali Hadiashar, Eric King, David Entrikin, Wai Lang Lee
  • Publication number: 20190173486
    Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.
    Type: Application
    Filed: October 29, 2018
    Publication date: June 6, 2019
    Inventors: Jianping Wen, Ali Hadiashar, Eric King, David Entrikin, Wai Lang Lee
  • Patent number: 10224952
    Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: March 5, 2019
    Assignee: AVNERA CORPORATION
    Inventors: Jianping Wen, Ali Hadiashar, Eric King, David Entrikin, Wai Lang Lee
  • Publication number: 20170250703
    Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.
    Type: Application
    Filed: April 18, 2017
    Publication date: August 31, 2017
    Inventors: Jianping Wen, Ali Hadiashar, Eric King, David Entrikin, Wai Lang Lee
  • Patent number: 9628106
    Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: April 18, 2017
    Assignee: AVNERA CORPORATION
    Inventors: Jianping Wen, Ali Hadiashar, Eric King, David Entrikin, Wai Lang Lee