Abstract: A technique for improving the thermal power dissipation of an integrated circuit includes reducing the thermal resistivity of the integrated circuit by increasing heat transfer in vertical and/or lateral directions. These results are achieved by increasing the surface area of the backside and/or the surface area of the lateral sides of the integrated circuit die. In some embodiments of the invention, an integrated circuit includes circuit elements formed closer to a first surface of a semiconductor substrate than to a second surface of the semiconductor substrate. The semiconductor substrate has a varying profile that substantially increases the surface area of a thermal interface formed on the second surface as compared to the second surface being substantially planar. A maximum depth of the profile is less than the thickness of the semiconductor substrate.

Abstract: Semiconductor die analysis is enhanced via a method and system that use a heater having a plurality of heating elements to heat a selected portion of the die. According to an example embodiment of the present invention, the heater is thermally coupled to the die, and the die is operated while at least one of the plurality of heating elements heats a portion of the die. A response is detected and used to analyze the die. The present invention makes possible selective heating of the die in a manner that is readily controllable and implemented. Die analysis, including, for example, critical timing path analysis, is enhanced by this ability to controllably heat the die.

Abstract: Substrate removal for analysis of a semiconductor die is enhanced via a method and system for heating the die. According to an example embodiment of the present invention, a plurality of heating elements are formed in a semiconductor die. The die is operated while at least one of the plurality of heating elements heats a portion of the die adjacent the heating element. A response to the heating is detected and used to analyze the die. The present invention makes possible selective heating of the die in a manner that is readily controllable and implemented. Die analysis, including, for example, critical timing path analysis, is enhanced by this ability to controllably heat the die.

Abstract: A method and apparatus mechanism for testing data processing devices are implemented. The test mechanism isolates critical paths by correlating a scanning microscope image with a selected speed path failure. A trigger signal having a preselected value is generated at the start of each pattern vector. The sweep of the scanning microscope is controlled by a computer, which also receives and processes the image signals returned from the microscope. The value of the trigger signal is correlated with a set of pattern lines being driven on the DUT. The trigger is either asserted or negated depending the detection of a pattern line failure and the particular line that failed. In response to the detection of the particular speed path failure being characterized, and the trigger signal, the control computer overlays a mask on the image of the device under test (DUT).