Abstract: A system including an optical engine. In some embodiments, the system includes an integrated circuit in a first-level package, and the system includes the optical engine, in the first-level package, and the optical engine includes an electro-optical chip.

Abstract: A system including an optical engine. In some embodiments, the system includes an integrated circuit in a first-level package, and the system includes the optical engine, in the first-level package, and the optical engine includes an electro-optical chip.

Abstract: Apparatus and methods are provide for a multichannel clock and data recovery (CDR) device that shares information between channels. In an example, a multiple channel communication circuit can include a plurality of clock and data recovery (CDR) circuits, each CDR circuit of the plurality of CDR circuits associated with a channel of the multiple channel communication circuit. In certain examples, each CDR circuit can be configured to detect an incoming stream of data from the channel, to determine a setting of one or more parameters for correctly sampling the data from the incoming stream, and to share an indication of the setting of the one or more parameters to an adjacent CDR circuit of the plurality of CDR circuits.

Abstract: Apparatus and methods are provide for frame synchronization and clock and data recovery. In an example, a method can include receiving initial data of a stream of information, sampling the stream of information a plurality of times per unit interval to provide a plurality of sample intervals, integrating transition information for each sample interval, and selecting a sampling phase to sample each symbol of the stream of data using the integrated transition information.

Abstract: Apparatus and methods are provide for frame synchronization and clock and data recovery. In an example, a method can include receiving initial data of a stream of information, sampling the stream of information a plurality of times per unit interval to provide a plurality of sample intervals, integrating transition information for each sample interval, and selecting a sampling phase to sample each symbol of the stream of data using the integrated transition information.

Abstract: A given reference pattern is written on bit patterned media that has an initial reference pattern already disposed thereon. A write phase and frequency is detected based on the initial reference pattern and the given reference pattern is written on the bit patterned media at the detected write phase and frequency.

Abstract: This disclosure is related to measurement of latency in data paths. A latency measurement may be accomplished by calculating a roundtrip write-to-read latency based on generating a write signal and receiving a read signal approximately simultaneously. The read signal may be based on a coupling between a write element and read element. A device setting may then be adjusted based on the calculated roundtrip write-to-read latency. Further, a read/write mechanism that is used to write user data to and read user data from a data storage medium may be used to determine the roundtrip write-to-read latency. Even further, the roundtrip write-to-read latency may be determined in real-time as the data storage device is in operation.

Abstract: Apparatus and method for write delay stabilization. A write driver is adapted to output bipolar write currents to write data to a memory. A preconditioning circuit is adapted to output first and second thermal preconditioning currents through the write driver to stabilize a write delay associated with the write driver to a steady-state level prior to the writing of data to the memory.

Abstract: Apparatus and method for write delay stabilization. A write driver is adapted to output bipolar write currents to write data to a memory. A preconditioning circuit is adapted to output first and second thermal preconditioning currents through the write driver to stabilize a write delay associated with the write driver to a steady-state level prior to the writing of data to the memory.

Abstract: This disclosure is related to measurement of latency in data paths. A latency measurement may be accomplished by calculating a roundtrip write-to-read latency based on generating a write signal and receiving a read signal approximately simultaneously. The read signal may be based on a coupling between a write element and read element. A device setting may then be adjusted based on the calculated roundtrip write-to-read latency. Further, a read/write mechanism that is used to write user data to and read user data from a data storage medium may be used to determine the roundtrip write-to-read latency. Even further, the roundtrip write-to-read latency may be determined in real-time as the data storage device is in operation.

Abstract: A given reference pattern is written on bit patterned media that has an initial reference pattern already disposed thereon. A write phase and frequency is detected based on the initial reference pattern and the given reference pattern is written on the bit patterned media at the detected write phase and frequency.