Abstract: A clock line over-protection circuit (28) carried on an interface card (16) for interfacing synchronous clock line (20), power line (22), DC common line (24) and data line (26) between a host computer (12) and a plurality of data link modules (14) with a plurality of associated controlled devices (18) including a series resistor (52) interconnected between a clock disable switch (52) and a clock signal generating amplifier (48) and a current sensor circuit (64, FIG. 3) connected across the series resistor (50) to produce a current sensor signal on an output (62). The current sensor signal is integrated by an over-current protection circuit (58, FIG. 4) to produce an over-current detection signal that varies with the difference in the clock line current magnitude during clock signal phases of opposite polarity.