Patents by Inventor David F. Beigel

David F. Beigel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5637901
    Abstract: A diode-connected transistor device for IC protection against electrostatic discharge (ESD) that functions as a transistor in the active region during an ESD event. The device cell includes an annular collector at the outer reaches of the cell, a circular base diffusion concentric with the collector, and an annular emitter near the outer edge of the base. The base and emitter regions are connected together by metallization external to the transistor cell. With the base contact enclosed by the annular emitter, during an ESD spike the initial reverse bias current flow is from the collector, under the emitter diffusion and out of the base contact. Eventually, as the magnitude of the ESD spike increases, the reverse biased current becomes sufficient to locally forward bias the base-emitter junction changing the primary ESD current path from collector to base, to collector to emitter, thus lowering the ESD current density in the active base-collector junction.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: June 10, 1997
    Assignee: Analog Devices, Inc.
    Inventors: David F. Beigel, Edward L. Wolfe, William A. Krieger
  • Patent number: 5594266
    Abstract: An ESD protective clamp device comprised of a two-terminal diode formed in an isolated chip cell. The lower part of this chip cell region contains a buried layer of silicon with P-type dopant, and the upper part is an epitaxial layer also with P-type dopant. An annular (ring-shaped) anode plug segment is formed at the outer reaches of the epitaxial layer with P+ doping. At the interior central region is an N-type plug circular in horizontal cross-section and concentric with the annular plug. This central plug serves as the cathode. Electrical connections are made to anode and cathode to provide interconnection with an IC circuit with a MOM capacitor to be protected.
    Type: Grant
    Filed: October 20, 1995
    Date of Patent: January 14, 1997
    Assignee: Analog Devices, Incorporated
    Inventors: David F. Beigel, William A. Krieger, Susan L. Feindt
  • Patent number: 5477078
    Abstract: An ESD protective clamp device comprised of a two-terminal diode formed in an isolated chip cell. The lower part of this chip cell region contains a buried layer of silicon with P-type dopant, and the upper part is an epitaxial layer also with P-type dopant. An annular (ring-shaped) anode plug segment is formed at the outer reaches of the epitaxial layer with P+ doping. At the interior central region is an N-type plug circular in horizontal cross-section and concentric with the annular plug. This central plug serves as the cathode. Electrical connections are made to anode and cathode to provide interconnection with an IC circuit with a MOM capacitor to be protected.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: December 19, 1995
    Assignee: Analog Devices, Incorporated
    Inventors: David F. Beigel, William A. Krieger, Susan L. Feindt
  • Patent number: 5446302
    Abstract: A diode-connected transistor device for IC protection against electrostatic discharge (ESD) that functions as a transistor in the active region during an ESD event. The device cell includes an annular collector at the outer reaches of the cell, a circular base diffusion concentric with the collector, and an annular emitter near the outer edge of the base. The base and emitter regions are connected together by metallization external to the transistor cell. With the base contact enclosed by the annular emitter, during an ESD spike the initial reverse bias current flow is from the collector, under the emitter diffusion and out of the base contact. Eventually, as the magnitude of the ESD spike increases, the reverse biased current becomes sufficient to locally forward bias the base-emitter junction changing the primary ESD current path from collector to base, to collector to emitter, thus lowering the ESD current density in the active base-collector junction.
    Type: Grant
    Filed: December 14, 1993
    Date of Patent: August 29, 1995
    Assignee: Analog Devices, Incorporated
    Inventors: David F. Beigel, Edward L. Wolfe, William A. Krieger