Abstract: A distributed driver for an optic signal generator comprising amplifier cells having an amplifier cell input configured to receive the input signal and amplifiers configured to amplify the received signal to create an amplified signal, and an amplifier cell output. The distributed driver also includes an input path connected to the amplifier cell input to receive the input signal and distribute the input signal to the two or more amplifier cells. The input path includes one or more buffers configured to introduce a delay into the input signal. An output path is provided and connects to the amplifier cell outputs of the two or more amplifier cells. The output path is configured to receive the amplified signal and the output path includes one or more inductors that incorporated with the parasitic capacitance from the two or more amplifier cells form the LC segments of an artificial transmission line.

Abstract: A rehabilitation device for exercising a human appendage comprises a housing defining a reservoir and a thermally controllable viscous fluid contained within the reservoir, the thermally controllable viscous fluid having a temperature and a viscosity. The thermally controllable viscous fluid experiences an apparent change in viscosity when exposed to a change in temperature. A heating apparatus is provided for increasing the temperature of the thermally controllable viscous fluid, and a cooling apparatus is provided for decreasing the temperature of the thermally controllable viscous fluid. A temperature control apparatus is provided for selectively increasing or decreasing the temperature of the thermally controllable viscous fluid and thereby decreasing or increasing the viscosity of the thermally controllable viscous fluid.

Abstract: A rehabilitation device for exercising a human appendage comprises a housing defining a reservoir and a thermally controllable viscous fluid contained within the reservoir, the thermally controllable viscous fluid having a temperature and a viscosity. The thermally controllable viscous fluid experiences an apparent change in viscosity when exposed to a change in temperature. A heating apparatus is provided for increasing the temperature of the thermally controllable viscous fluid, and a cooling apparatus is provided for decreasing the temperature of the thermally controllable viscous fluid. A temperature control apparatus is provided for selectively increasing or decreasing the temperature of the thermally controllable viscous fluid and thereby decreasing or increasing the viscosity of the thermally controllable viscous fluid.

Abstract: Methods, apparatus, systems, and articles of manufacture are described to facilitate access control in memory. An example method includes accessing state values stored in non-volatile memory, the state values corresponding to a state of the non-volatile memory; responsive to obtaining a request to enter a diagnostic mode, authenticating credentials corresponding to the request; determining the state of the non-volatile memory based on the state values; and determining whether to permit or prohibit access to the non-volatile memory based on the determined state.

Abstract: In described examples, a circuit device includes a memory having a set of memory ranges and a processor device coupled to the memory. The processor device is configured to fetch programmable instructions from the memory, and configured to determine memory access and execution permissions for the programmable instructions. Permissions are determined responsive to a set of a set of access protection registers (APRs) and a set of LINKs. The APRs each specify permissions for a respective associated memory range. The LINKs are each associated with a respective subset of the APRs. Each of the APRs specifies access protection responsive to each LINK. Each of the programmable instructions corresponds to the APR (source APR) associated with a memory range in which the programmable instruction is stored, and corresponds to the LINK (source LINK) associated with the respective source APR.

Abstract: In described examples, an integrated circuit (IC) includes a memory and a processor coupled to the memory. The processor is configured to execute a discontinuity instruction, which specifies a memory address, to transition from executing according to a first stack pointer to executing according to a second stack pointer. The first stack pointer is copied from an active stack register to an inactive first stack pointer register. The processor determines whether the specified memory address stores a stack entry instruction that corresponds to the discontinuity instruction. If it does, the second stack pointer is copied from the inactive second stack pointer register to the active stack register, and the processor executes the stack entry instruction and begins execution according to the second stack pointer.

Abstract: In described examples, a circuit device includes a memory having a set of memory ranges, a logic circuit, access protection registers (APRs), ZONE debug permission registers, and a processor coupled to the memory. Each APR stores memory access permissions for an associated memory range. Each ZONE debug permission register stores debug permissions for a ZONE. Each ZONE is associated with a subset of the APRs so that each APR is associated with one ZONE. The processor executes a debug instruction to control the circuit device as follows. An APR associated with a memory address in the debug instruction provides a first permission to a first logic circuit input. The ZONE debug permission registers provide a second permission responsive to a credential to a second logic circuit input. The processor performs a debug action responsive to the debug instruction and a logic circuit output.

Abstract: A phase interpolator with a DAC outputting a first and second value responsive to a control code. A first current mirror generates a first current proportional to the first value. A second current mirror generates a second current proportional to the second value. A first FET pair comprising a first and second FET such that the source terminals of the first FET and the second FET are electrically connected and connect to the first current mirror. A second FET pair comprising a third and fourth FET such that the source terminals of the third FET and the fourth FET are electrically connected and connect to the second current mirror. A first terminal outputs a phase adjusted clock signal as compared to the clock signal, from the first FET and the third FET. A second terminal outputs an inverted phase adjusted clock signal, from the second FET and the fourth FET.

Abstract: The present invention provides compounds of Formula (I), as well as pharmaceutically acceptable salts thereof: wherein X1, X2, X3, R3, Ring A and Ring B are as described herein. The compounds have affinity for ?5-subunit-containing GABAA receptors. The invention further provides the manufacture of the compounds of formula (I), pharmaceutical compositions comprising the compounds and their use as medicaments for the treatment of diseases and disorders associated with ?5-GABAA receptors, including depression and cognitive impairment, for example, cognitive impairment associated with a psychotic disorder such as schizophrenia.

Abstract: A graphical user interface for displaying and managing information structures, the graphical user interface comprising at least one Viewport, at least one concept space in the at least one Viewport and at least one container item displayed in the at least one concept space, the container item being adapted to include a concept space branch adapted to be connected to another concept space, wherein a user can interact with the at least one container item to create a link to an item, the interaction with the at least one container item comprising a zoom-in and a zoom-out function for respectfully increasing functions associated with the at least one container item or decreasing functions associated with the at least one container item.

Abstract: A baseline wander and offset correction system having inputs configured to receive input signals to be transmitted. Also part of the system is a driver circuit configured to receive and amplify the input signals. The driver circuit is configured with one or more transistors having an optional back bias terminal. A replica circuit receives the input signals and responsive thereto, generates back bias signals which are provided to the back bias terminal of the one or more transistors to change the back bias in response to the input signals having consecutive one values or consecutive zero values. This reduces the size of the one or more AC coupling capacitors located between the driver circuit and a channel. An embodiment may store back bias values in a memory. The back bias values are processed by DAC to generate the back bias signals for offset correction.

Abstract: A multi-stage driver circuit has a transmission line coupled to an output of the multi-stage driver circuit. The transmission line has inductive elements and programmable capacitive elements selected to shape the transmitted data signal. The programmable capacitive elements have a first capacitor with a first terminal coupled to a first power supply conductor, and a first transistor with a first conduction terminal coupled to a second terminal of the first capacitor, and a second conduction terminal coupled to a second power supply conductor. The programmable capacitive elements have a register with a first output coupled to a control terminal of the first transistor. The programmable capacitive elements are selected to shape the transmitted data signal by observing operational dynamics of the multi-stage driver circuit.

Abstract: A distributed driver for an optic signal generator comprising amplifier cells having an amplifier cell input configured to receive the input signal and amplifiers configured to amplify the received signal to create an amplified signal, and an amplifier cell output. The distributed driver also includes an input path connected to the amplifier cell input to receive the input signal and distribute the input signal to the two or more amplifier cells. The input path includes one or more buffers configured to introduce a delay into the input signal. An output path is provided and connects to the amplifier cell outputs of the two or more amplifier cells. The output path is configured to receive the amplified signal and the output path includes one or more inductors that incorporated with the parasitic capacitance from the two or more amplifier cells form the LC segments of an artificial transmission line.

Abstract: A baseline wander and offset correction system having inputs configured to receive input signals to be transmitted. Also part of the system is a driver circuit configured to receive and amplify the input signals. The driver circuit is configured with one or more transistors having an optional back bias terminal. A replica circuit receives the input signals and responsive thereto, generates back bias signals which are provided to the back bias terminal of the one or more transistors to change the back bias in response to the input signals having consecutive one values or consecutive zero values. This reduces the size of the one or more AC coupling capacitors located between the driver circuit and a channel. An embodiment may store back bias values in a memory. The back bias values are processed by DAC to generate the back bias signals for offset correction.

Abstract: A phase interpolator with a DAC outputting a first and second value responsive to a control code. A first current mirror generates a first current proportional to the first value. A second current mirror generates a second current proportional to the second value. A first FET pair comprising a first and second FET such that the source terminals of the first FET and the second FET are electrically connected and connect to the first current mirror. A second FET pair comprising a third and fourth FET such that the source terminals of the third FET and the fourth FET are electrically connected and connect to the second current mirror. A first terminal outputs a phase adjusted clock signal as compared to the clock signal, from the first FET and the third FET. A second terminal outputs an inverted phase adjusted clock signal, from the second FET and the fourth FET.

Abstract: Systems and methods for passively processing a payment for an activity that leverages location data of a user participating in the activity. User data is received, the user data including a plurality of user location points and a time associated with each of the plurality of user location points. An activity is determined, the activity associated with the user based on the user data, wherein the activity is associated with at least one of transportation and attendance at a venue. An instance of the activity is identified and a payment amount for the user is processed based on the instance of the activity.

Abstract: A graphical user interface for displaying and managing information structures, the graphical user interface comprising at least one Viewport, at least one concept space in the at least one Viewport and at least one container item displayed in the at least one concept space, the container item being adapted to include a concept space branch adapted to be connected to another concept space, wherein a user can interact with the at least one container item to create a link to an item, the interaction with the at least one container item comprising a zoom-in and a zoom-out function for respectfully increasing functions associated with the at least one container item or decreasing functions associated with the at least one container item.

Abstract: A serializer clock delay optimization system comprising a multiplexer configured to receive two or more low-rate data signals and a multiplexer control signal. The multiplexer generates a full-rate data signal by combining the two or more low-rate data signals such that the multiplexer control signal determines sampling time of the low-rate data signals. A data monitor monitors and evaluates the full-rate data signal to generate a quality value representing the quality of the full-rate data signal. The quality of the full-rate data signal is based on the accuracy of the sampling time of the low-rate data signals. A delay controller processes the quality value to generate a delay control signal or value. A delay receives a clock signal and the delay control signal or value. Responsive to the delay control signal or value, the delay modifies the timing of the clock signal to create the multiplexer control signal.

Abstract: Systems and methods for passively processing a payment for an activity that leverages location data of a user participating in the activity. User data is received, the user data including a plurality of user location points and a time associated with each of the plurality of user location points. An activity is determined, the activity associated with the user based on the user data, wherein the activity is associated with at least one of transportation and attendance at a venue. An instance of the activity is identified and a payment amount for the user is processed based on the instance of the activity.

Abstract: A system and method to level-shift multiple signals from a first voltage domain to a second voltage domain with minimized silicon area. A level-shifting system may be organized by implementing a static level-shifter coupled to a plurality of dynamic level-shifters. The static level-shifter may provide a voltage control signal for each of the dynamic level-shifters. Each of the dynamic level-shifters may level-shift an individual input signal from a first voltage domain to a second voltage domain.