Abstract: The present disclosure provides compounds or pharmaceutically acceptable salts thereof, e.g., radioimmunoconjugates including a chelating moiety or a metal complex thereof, a linker, and an antibody or antigen-binding fragment thereof targeting STEAP2. The present disclosure also provides pharmaceutical compositions of such compounds or pharmaceutically acceptable salts thereof and methods of treatment for conditions, e.g., cancer, using such compounds, pharmaceutically acceptable salts thereof, or pharmaceutical compositions.

Abstract: The present invention features, inter alia, methods of treating a patient having chronic spontaneous urticaria (CSU) by administering an anti-tryptase antibody (e.g., anti-tryptase beta antibody) to the patient, anti-tryptase antibodies (e.g., anti-tryptase beta antibodies) for use in treating CSU, and uses of anti-tryptase antibodies (e.g., anti-tryptase beta antibodies), e.g., in the manufacture of medicaments for treating CSU.

Abstract: The application describes a method of treating chronic obstructive pulmonary disease (COPD) in a patient comprising administering 476 mg of an ST2 antagonist to the patient on Day 1 of a treatment period. The application also describes methods of treating or preventing frequency of moderate to severe exacerbations in a patient having COPD comprising administering an effective amount of an ST2 antagonist to achieve a clinical improvement of at least 10%, at least 20%, at least 21%, at least 22%, at least 25%, at least 30%, at least 35%, at least 40% or at least 45% annualized exacerbation rate reduction than standard of care (SOC).

Abstract: A circular First-In-First-Out (FIFO) Buffer is provided as an intuitive interface between synchronous domains and asynchronous domains by incorporating flow control and standard synchronizers to allow for serialization and deserialization that can be carried out as an asynchronous-to-synchronous transition, a synchronous-to-asynchronous transition, or even a fully asynchronous circular transition. Each of these configurations may also include single read or multiple-read operations.

Abstract: A hybrid asynchronous network-on-chip (NoC) optimized for artificial intelligence workloads utilizes a “tile” layout methodology with a plurality of tiles, each tile including an asynchronous node with a plurality of input ports and output ports for communicating with adjacent asynchronous nodes on adjacent tiles, along with a processor input port and processor output port configured to transport data from an asynchronous processor, but capable of being customized to transport data between a synchronous processor through the implementation of modular synchronous-to-asynchronous and asynchronous-to-synchronous first-in-first-out (FIFO) buffers. The asynchronous NoC is able to efficiently satisfy the interconnect traffic requirement of modern machine learning systems, eliminating the need for a global clock distribution and enabling unlimited scalability while providing high throughput and minimal latency performance.

Abstract: Systems and methods for providing Chronos Channel interconnects in an ASIC are provided. Chronos Channels rely on a reduced set of timing assumptions and are robust against delay variations. Chronos Channels transmit data using delay insensitive (DI) codes and quasi-delay-insensitive (QDI) logic. Chronos Channels are insensitive to all wire and gate delay variations, but for those belonging to a few specific forking logic paths called isochronic forks. Chronos Channels use temporal compression in internal paths to reduce the overheads of QDI logic and efficiently transmit data. Chronos Channels are defined by a combination of a DI code, a temporal compression ratio and hardware.

Abstract: Systems and methods for providing input and output ports to connect to channels are provided. Input and output ports are the basic building blocks to create more complex data routing IP blocks. By aggregating these modular ports in different ways, different implementations of crossbar or Network on Chip (NoC) can be implemented, allowing flexible routing structure while maintaining all the benefits of channels such as robustness against delay variation, data compression and simplified timing assumptions.

Abstract: Systems and methods for providing Chronos Channel interconnects in an ASIC are provided. Chronos Channels rely on a reduced set of timing assumptions and are robust against delay variations. Chronos Channels transmit data using delay insensitive (DI) codes and quasi-delay-insensitive (QDI) logic. Chronos Channels are insensitive to all wire and gate delay variations, but for those belonging to a few specific forking logic paths called isochronic forks. Chronos Channels use temporal compression in internal paths to reduce the overheads of QDI logic and efficiently transmit data. Chronos Channels are defined by a combination of a DI code, a temporal compression ratio and hardware.

Abstract: This application discloses circuits and apparatus configured to measure performance of asynchronous circuits by injecting data in to inputs of asynchronous circuits and consuming data from the outputs without interfering in the functionality of the asynchronous circuits. This application also discloses systems and methods for assessing the performance of asynchronous channels and/or IP blocks by providing an unambiguous performance value which can be used for performance analysis and comparison.

Abstract: Systems and methods for providing input and output ports to connect to channels are provided. Input and output ports are the basic building blocks to create more complex data routing IP blocks. By aggregating these modular ports in different ways, different implementations of crossbar or Network on Chip (NoC) can be implemented, allowing flexible routing structure while maintaining all the benefits of channels such as robustness against delay variation, data compression and simplified timing assumptions.

Abstract: This application discloses circuits and apparatus configured to measure performance of asynchronous circuits by injecting data in to inputs of asynchronous circuits and consuming data from the outputs without interfering in the functionality of the asynchronous circuits. This application also discloses systems and methods for assessing the performance of asynchronous channels and/or IP blocks by providing an unambiguous performance value which can be used for performance analysis and comparison.

Abstract: Systems and methods for application specific integrated circuit design using Chronos Links are disclosed. A Chronos Link is an ASIC on-chip and off-chip interconnect communication protocol that allows interfaces to transmit and receive information. The protocol may utilize messages or signals to indicate the availability and/or readiness of information to be exchanged between a producer and a consumer allowing the communication to be placed on hold and to be resumed seamlessly. A method includes inserting gaskets and channel repeaters connected to interfaces of multiple intellectual property (IP) blocks in order to replace traditional links with Chronos Links; performing simplified floorplanning; performing simplified placement; performing simplified clock tree synthesis (CTS) and routing; and performing simplified timing closure, where timing estimates are based on a double nature arc abstraction.

Abstract: Systems and methods for providing input and output ports to connect to channels are provided. Input and output ports are the basic building blocks to create more complex data routing IP blocks. By aggregating these modular ports in different ways, different implementations of crossbar or Network on Chip (NoC) can be implemented, allowing flexible routing structure while maintaining all the benefits of channels such as robustness against delay variation, data compression and simplified timing assumptions.

Abstract: This application discloses circuits and apparatus configured to measure performance of asynchronous circuits by injecting data in to inputs of asynchronous circuits and consuming data from the outputs without interfering in the functionality of the asynchronous circuits. This application also discloses systems and methods for assessing the performance of asynchronous channels and/or IP blocks by providing an unambiguous performance value which can be used for performance analysis and comparison.

Abstract: Systems and methods for providing input and output ports to connect to channels are provided. Input and output ports are the basic building blocks to create more complex data routing IP blocks. By aggregating these modular ports in different ways, different implementations of crossbar or Network on Chip (NoC) can be implemented, allowing flexible routing structure while maintaining all the benefits of channels such as robustness against delay variation, data compression and simplified timing assumptions.

Abstract: This application discloses circuits and apparatus configured to measure performance of asynchronous circuits by injecting data in to inputs of asynchronous circuits and consuming data from the outputs without interfering in the functionality of the asynchronous circuits. This application also discloses systems and methods for assessing the performance of asynchronous channels and/or IP blocks by providing an unambiguous performance value which can be used for performance analysis and comparison.

Abstract: Systems and methods for providing input and output ports to connect to channels are provided. Input and output ports are the basic building blocks to create more complex data routing IP blocks. By aggregating these modular ports in different ways, different implementations of crossbar or Network on Chip (NoC) can be implemented, allowing flexible routing structure while maintaining all the benefits of channels such as robustness against delay variation, data compression and simplified timing assumptions.

Abstract: Systems and methods for providing input and output ports to connect to channels are provided. Input and output ports are the basic building blocks to create more complex data routing IP blocks. By aggregating these modular ports in different ways, different implementations of crossbar or Network on Chip (NoC) can be implemented, allowing flexible routing structure while maintaining all the benefits of channels such as robustness against delay variation, data compression and simplified timing assumptions.

Abstract: This application discloses the implementation of a self-timed IP with optional clock-less compression and decompression at the boundaries. It also discloses system and methods for application specific integrated circuits to convert RTL code and timing constraints to self-timed circuitry with optional clock-less compression and decompression at the boundaries.

Abstract: Systems and methods for providing Chronos Channel interconnects in an ASIC are provided. Chronos Channels rely on a reduced set of timing assumptions and are robust against delay variations. Chronos Channels transmit data using delay insensitive (DI) codes and quasi-delay-insensitive (QDI) logic. Chronos Channels are insensitive to all wire and gate delay variations, but for those belonging to a few specific forking logic paths called isochronic forks. Chronos Channels use temporal compression in internal paths to reduce the overheads of QDI logic and efficiently transmit data. Chronos Channels are defined by a combination of a DI code, a temporal compression ratio and hardware.