Patents by Inventor David Fraboulet

David Fraboulet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7217946
    Abstract: This invention relates to a process for manufacturing nanowire structures, the process comprising the following steps: manufacture of a thin semiconductor film (1) extending between a first terminal (4) and a second terminal (5), and passage of a current between the first and the second terminals so as to form at least one continuous overthickness (R1, R2, R3) in the thin semiconductor film by migration of a fraction of the semiconductor material, under the action of the current, the continuous overthickness being formed along the direction of the current that passes through the film.
    Type: Grant
    Filed: October 2, 2003
    Date of Patent: May 15, 2007
    Assignee: Commissariat a l'Energie Atomique
    Inventors: David Fraboulet, Jacques Gautier, Didier Tonneau, Nicolas Clement, Vincent Bouchiat
  • Publication number: 20060286788
    Abstract: This invention relates to a process for manufacturing nanowire structures, the process comprising the following steps: manufacture of a thin semiconductor film (1) extending between a first terminal (4) and a second terminal (5), and passage of a current between the first and the second terminals so as to form at least one continuous overthickness (R1, R2, R3) in the thin semiconductor film by migration of a fraction of the semiconductor material, under the action of the current, the continuous overthickness being formed along the direction of the current that passes through the film.
    Type: Application
    Filed: October 2, 2003
    Publication date: December 21, 2006
    Inventors: David Fraboulet, Jacques Gautier, Didier tonneau, Nicolas Clement, Vincent Bouchiat
  • Patent number: 7041539
    Abstract: A method produces a microstructure comprising an island of material confined between two electrodes forming barriers, the island (30) of material having lateral flanks running parallel to and lateral flanks running perpendicular to the barriers, wherein the lateral flanks of the island are defined by etching of at least one layer (16), called the template layer, and the barriers are formed by damascening. The method includes (a) a first etching of the template layer using a first etching mask having at least one filiform part, and (b) a second etching of the template layer, subsequent to the first etching, using a second etching mask also having at least one filiform part, oriented in a direction forming a non-zero angle with a direction of orientation of the filiform part of the first mask, in the vicinity of the site of formation of the island.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: May 9, 2006
    Assignees: Commissariat a l'Energie Atomique, STMicroelectronics
    Inventors: David Fraboulet, Denis Mariolle, Yves Morand
  • Patent number: 6998310
    Abstract: This invention relates to a process for a manufacturing a Coulomb blockade transistor. The process comprises the following steps in sequence: deposition on an insulating substrate of a source layer, a tunnel-insulating layer and an alternating stack of at least one conducting layer and at least one insulating layer, a first etching of the stack to form a filiform tab, coating of the filiform tab with an electrically insulating coating material, a second etching of the tab of the stack to form a pillar, the second etching preserving the coating material to define a groove on each side of the pillar, the formation of at least one isolated grid in the groove, and the formation of a drain in contact with one end of the pillar opposite the source layer, through at least one tunnel-insulating layer.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: February 14, 2006
    Assignee: Commissariat a l'Energie Atomique
    Inventors: David Fraboulet, Simon Deleonibus
  • Publication number: 20040238808
    Abstract: This invention relates to a Coulomb blockade transistor comprising the following on a substrate:
    Type: Application
    Filed: March 30, 2004
    Publication date: December 2, 2004
    Inventors: David Fraboulet, Simon Deleonibus
  • Publication number: 20040075123
    Abstract: The invention relates to a method for producing a microstructure comprising an island (30) of material confined between two electrodes (32) forming barriers; the island of material having lateral flanks running parallel and perpendicular to the barriers, characterized in that the lateral flanks of the island are defined by etching of at least one layer (16), called the template layer, and the barriers are formed by damascening.
    Type: Application
    Filed: December 4, 2003
    Publication date: April 22, 2004
    Inventors: David Fraboulet, Denis Mariolle, Yves Morand