Abstract: An integrated circuit package and method of fabrication are described. The integrated circuit package includes a lead frame having a first surface and a second opposing surface and a semiconductor die having a first, active surface in which circuitry is disposed and a second opposing surface attached to the first surface of the lead frame. A magnet attached to the second surface of the lead frame has a non-contiguous central region and at least one channel extending laterally from the central region. An overmold material forms an enclosure surrounding the magnet, semiconductor die, and a portion of the lead frame.

Abstract: Querying of time-aware metrics time series includes receiving a query, the query comprising a set of query metadata and a query time range. It further includes, based at least in part on the set of query metadata and the query time range, selecting a time series from a plurality of metrics time series. Each metrics time series in the plurality of metrics time series is associated with a set of metadata and an active interval of time. A set of metadata associated with the selected time series matches the set of query metadata, and an active interval of time associated with the selected metrics time series intersects with the query time range. The selected metrics time series is returned.

Abstract: There is provided a method and apparatus for the analysis of a ballistocardiogram signal. The method comprises detecting heart beats in the BCG signal by locating typical features of a heart beat for a user in the BCG signal, the typical features of the heart beat having been obtained during a training step.

Abstract: A benchmark tester retrieves a voltage margin that corresponds to a device that a system includes. The voltage margin indicates an additional amount of voltage to apply to a nominal voltage that, when added, results in the device operating at a power limit while executing a worst-case power workload. Next, the benchmark tester (or thermal power management device) sets an input voltage for the device to a value equal to the sum of the voltage margin and the nominal voltage. The benchmark tester then dynamically benchmark tests the system, which includes adjusting the device's frequency and input voltage while ensuring that the device does not exceed the device's power limit. In turn, the benchmark tester records a guaranteed minimum performance boost for the system based upon a result of the benchmark testing.

Abstract: There is provided a method for analyzing a ballistocardiogram signal to determine a heart rate, the method comprising: determining an initial time estimate for a first heart beat in the ballistocardiogram signal; computing, iteratively, estimates for subsequent heart beats in the ballistocardiogram signal using the initial time estimate; wherein each iteration in the step of computing comprises evaluating a target function that comprises a weighted sum of a plurality of scoring functions; and wherein each iterative step of computing estimates for subsequent heart beats in the ballistocardiogram signal is limited to a target interval after the time estimate found in the previous iterative step of computing.

Abstract: A benchmark tester retrieves a voltage margin that corresponds to a device that a system includes. The voltage margin indicates an additional amount of voltage to apply to a nominal voltage that, when added, results in the device operating at a power limit while executing a worst-case power workload. Next, the benchmark tester (or thermal power management device) sets an input voltage for the device to a value equal to the sum of the voltage margin and the nominal voltage. The benchmark tester then dynamically benchmark tests the system, which includes adjusting the device's frequency and input voltage while ensuring that the device does not exceed the device's power limit. In turn, the benchmark tester records a guaranteed minimum performance boost for the system based upon a result of the benchmark testing.

Abstract: A method, an apparatus and computer instructions are provided for specifying multiple voltage domains of a signal and macros in a processor chip and validating physical implementation and interconnections of the signal and macros. A set of attributes is provided for designs to define multiple voltage domains of a signal and macros in a processor chip. A first validation mechanism is then provided to validate that no electrical or logical errors created by logical connections between macros as defined by the set of attributes. A translation mechanism is provided to translate logical voltage description to a physical netlist for designers to connect powers to macros and signals. A second validation mechanism is provided to validate physical implementation adhere to designers' intent according to the set of attributes defined in the logical design.