Abstract: Memory and logic error rates are predicted by breaking each transistor into theoretical “boxes” with differing sensitivities to ionizing radiation. The box dimensions and critical charge are determined using physics-based equations. The box dimensions and critical charge are used to calculate soft error rate (SER). This box method may be used to calculate SER due to an ion that simultaneously strikes two separate sensitive volumes in order to cause an upset. Additionally, the box method may used to predict upsets that occur when an ion strike pulls a circuit node below ground or above the positive power supply.

Abstract: A decision block is incorporated into a circuit design to provide hardening against single event upset and to store data. The decision block includes a storage element that stores data as long as inputs to the decision block remain constant. The decision block receives a first data input and second data input from redundant logic blocks or from logic blocks designed to provide complementary outputs. The decision block provides an output that is at a same logic level as the first data input if the two data inputs are at expected logic levels during normal operating conditions (i.e., no disturbances). The decision block provides an output that is at a same logic level as a previous output of the decision block if the two data inputs are not at expected logic levels during normal operating conditions.

Abstract: A method for modeling a circuit layout to determine behavior responsive to a radiation event is set forth. The method includes identifying a first portion of the circuit layout that includes at least one body region of a MOS transistor in the circuit layout, the at least one region having a width substantially equal to that of the MOS transistor. A first model corresponding to the first portion of the circuit layout is selected. A second portion of the circuit layout that includes at least a first region within a drain of the MOS transistor in the circuit layout is identified and an appropriate second model corresponding to the second portion of the circuit layout is selected, wherein the at least one second model includes at least one parasitic bipolar transistor.

Abstract: An apparatus and method for hardening a circuit against a single-event effect condition is provided. A first logic circuit outputs an output-signal event having a glitch impressed thereon. A glitch filter (i) receives the output-signal event, (ii) slows down a rate of change of the output-signal event by a given amount of time to produce a slowed output-signal event, and (iii) provides to a second logic circuit the slowed output-signal event. When a duration of the output-signal event is less than the given amount of time, the glitch filter prevents the slowed output-signal event from attaining an undesired-state threshold, which in turn prevents the second logic circuit from operating in an undesired state. An optional feedback module feeds a feedback-signal event without a glitch to the glitch filter. When the slowed output-signal event does not satisfy the undesired-state threshold, the feedback-signal event neutralizes the glitch impressed upon the output-signal event.

Abstract: A technique to read a stored state in a magnetoresistive random access memory (MRAM) device, such as a giant magneto-resistance (GMR) MRAM device or a tunneling magneto-resistance (TMR) device uses a bit line in an MRAM device that is segmented into a first portion and a second portion. An interface circuit compares the resistance of a first portion and a second portion of a first bit line to the resistance of a first portion and a second portion of a second bit line to determine the logical state of a cell in the first bit line. The interface circuit includes a reset circuit that selectively couples the outputs of the interface circuit together. A subsequent decoupling of the outputs allows cross-coupling within the interface circuit to latch the outputs to a logical state corresponding to the stored magnetic state, thereby allowing the stored state of a cell to be read.