Abstract: Briefly, in accordance with one embodiment of the invention, a system includes a memory array. The memory array comprises a first layer of memory cells overlying a second layer of memory cells and bit lined coupled to at least one memory cell in the first layer of memory cells and to at least one memory cell in the second layer of memory cell.

Abstract: Briefly, in accordance with one embodiment of the invention, a system includes a memory array. The memory array comprises a first layer of memory cells overlying a second layer of memory cells and bit lined coupled to at least one memory cell in the first layer of memory cells and to at least one memory cell in the second layer of memory cell.

Abstract: A ferroelectric memory device and method for reading such a device utilize capacitive coupling between a bit line and sense amplifier. The gain depends on a capacitance ratio rather than the absolute value of a capacitor. Ratiometric gain control reduces the gain variability of a sense amplifier, thereby allowing more accurate sensing. Attenuating the signal from an active bit line eliminates the need for high voltage devices in a sense amplifier arrangement.

Abstract: A ferroelectric memory device and method for reading such a device utilize capacitive coupling between a reference circuit and a sense amplifier. The amount of sneak charge canceled from a data bit line depends on the relative capacitances of a coupling capacitor and another capacitor used to integrate sneak charge from a reference bit line. The use of linear-responding components improves stability.

Abstract: A ferroelectric memory device and method for reading such a device utilize capacitive coupling between a bit line and sense amplifier. The gain depends on a capacitance ratio rather than the absolute value of a capacitor. Ratiometric gain control reduces the gain variability of a sense amplifier, thereby allowing more accurate sensing. Attenuating the signal from an active bit line eliminates the need for high voltage devices in a sense amplifier arrangement.

Abstract: A memory device to receive a value from a programmable register, the value defines an operational characteristic of the memory device.

Abstract: A state of a memory element in a memory device is accessed by conditioning a number of wordlines and an addressed one of a number of bitlines in the memory device. This causes an addressed one of the memory elements in the device to release a signal charge and an unaddressed one to release a sneak charge into the addressed bitline. This charge release causes the current in the addressed bitline to increase. This current is integrated, and integration is halted when a signal to sneak ratio of the addressed bitline is maximized. The integration yields a total bitline charge value that may be used to obtain a more accurate measurement of the released signal charge.

Abstract: A state of a memory element in a memory device is accessed by conditioning a number of wordlines and an addressed one of a number of bitlines in the memory device. This causes an addressed one of the memory elements in the device to release a signal charge and an unaddressed one to release a sneak charge into the addressed bitline. This charge release causes the current in the addressed bitline to increase. This current is integrated, and integration is halted when a signal to sneak ratio of the addressed bitline is maximized. The integration yields a total bitline charge value that may be used to obtain a more accurate measurement of the released signal charge.