Abstract: Methods and apparatuses for dynamically budgeting power usage in a data processing system. In one aspect, a data processing system, includes: one or more components including a first component; and a computing element, such as a microprocessor or a microcontroller, coupled to the first component to obtain one or more operating signals from the first component and to determine, based at least in part on the one or more operating signals, an estimate of a power consumption requirement of the one or more components for operating under the current condition. In one example, one or more sensors are used to determine information on actual power usage for a past period of time. A performance level setting of a second component, such as a CPU, a GPU, or a bus, is determined using the estimate and the information on the actual power usage, such as the operating voltage and frequency.

Abstract: One embodiment of the present invention provides a system that switches between frame buffers which are used to refresh a display. During operation, the system refreshes the display from a first frame buffer which is located in a first memory. Upon receiving a request to switch frame buffers for the display, the system reconfigures data transfers to the display so that the display is refreshed from a second frame buffer which is located in a second memory.

Abstract: One embodiment of the present invention provides a system that switches from a first graphics processor to a second graphics processor to drive a display. During operation, the system receives a request to switch a signal source which drives the display from the first graphics processor to the second graphics processor. In response to the request, the system first configures the second graphics processor so that the second graphics processor is ready to drive the display. Next, the system switches the signal source that drives the display from the first graphics processor to the second graphics processor, thereby causing the second graphics processor to drive the display.

Abstract: A communication method and a bus design for interconnecting a plurality of components in a ring configuration with segments of the bus chaining from one component to another so as to reduce the amount of global wiring between components. One of the components serves as a beginning and end of the ring and controls the operation of the bus by injecting command, address, and write data, at the beginning of the ring and gathering read data at the end of the ring. By chaining components, no bus signal needs to travel further than a single component-to-component hop in any bus cycle. The bus includes unidirectional signal lines that carry data objects and tags in one direction, and carry flow control in the opposite direction. Tags accompany each data object and determine how a component interprets the data object when received.

Abstract: Method, system, and computer program products for identifying potentially fraudulent receivers of digital content. A receiver authenticates to an auditing service with data that should be unique to the receiver. The auditing service detects when multiple receivers attempt to authenticate with the same data, suggesting that a receiver has been cloned or duplicated. The audit service also detects when a receiver authenticates improperly, suggesting an unsuccessful and unauthorized attempt to duplicate an authorized receiver. Individual receivers may be networked together. To help protect a receiver's authentication data from tampering, at least a portion of the data may be digitally signed with a private key. The audit service may then verify the digital signature with a corresponding public key. Varying the order in which data is signed or where the data is stored from one receiver or group of receivers to another may provide an additional level of security.

Abstract: Methods and voltage controlled oscillator designs that compensate for errors. The errors may be caused by variations, from one oscillator to another, in the voltage that produces a nominal frequency and variations in an overall voltage-to-frequency transfer function. A specific control voltage that produces the nominal frequency in a particular voltage controlled oscillator may be determined by comparing a reference frequency count to a variable frequency count for each of one or more control input voltages that are applied to the particular voltage controlled oscillator. The specific control voltage that produces the nominal frequency and other voltages that produce frequencies higher than the nominal frequency and that produce frequencies lower than the nominal frequency may be stored in a table.

Abstract: Methods and voltage controlled oscillator designs that compensate for errors. The errors may be caused by variations, from one oscillator to another, in the voltage that produces a nominal frequency and variations in an overall voltage-to-frequency transfer function. A specific control voltage that produces the nominal frequency in a particular voltage controlled oscillator may be determined by comparing a reference frequency count to a variable frequency count for each of one or more control input voltages that are applied to the particular voltage controlled oscillator. The specific control voltage that produces the nominal frequency and other voltages that produce frequencies higher than the nominal frequency and that produce frequencies lower than the nominal frequency may be stored in a table.

Abstract: An apparatus for generating control signals of a microprocessor includes a memory, for example, a pattern holding register storing an arbitrary bit pattern. The holding register can be loaded by software. A shift register is connected to receive the bit pattern from the pattern register. An output pin of the microprocessor receives each bit of the arbitrary bit pattern, directly, or indirectly via a bus interface unit, at a rate determined by a clock signal to generate control signals for arbitrary external devices.

Abstract: An operation of a processor is traced while fetching instructions from a memory to operate the processor. The tracing involves detecting an unpredictable fetching of instructions on the assumption that a predictable fetching can be reconstructed without any further input. The unpredictable fetching is identified as being due to either computable, conditional, or unanticipated events. Upon detecting the events, process control information, such as the next instruction to be fetched is recorded in a queue, and from the queue the information can be stored in a trace buffer. During reconstruction of the operation, the trace buffer, and the image including the instructions can be examined to analyze the real-time operation of the processor.

Abstract: A data flow of a processor is traced while accessing data stored in a memory and in a plurality of registers during operation of the processor. The tracing involves detecting an unpredictable accessing of data on the assumption that a predictable accessing can be reconstructed without any further input. The unpredictable accessing is identified by setting and clearing a trace bit associated with each of the registers according to identifying the accessing as direct memory-to-register, register-to-register, constant-to-register, and indirect memory. If a trace bit is set on a register storing data being used as a base address during the indirect memory acceding, data flow control information, such as the base address stored in the register being used during the indirect acceding is recorded in a queue, and from the queue the information can be stored in a trace buffer.

Abstract: A computer system includes a plurality of central processing units (CPUs) each of which has a direct napped cache memory. The system also includes a main memory, and one or more display frame buffers. The cache normally operates in a write back mode, whereby updated data is written back to main memory only when a cache block is reallocated to store a new block of data. A tag for each block of data stored in the cache includes a Shared flag which indicates whether the corresponding block of data may be stored in the cache of another CPU. When a block of data stored is modified, it is immediately written to main memory if the tag for that block has an enabled Shared flag. To make the cache operate in a write-through mode for blocks of image data, the system stores an enabled Shared flag in the cache whenever a block of frame buffer data is stored in the cache.

Abstract: An apparatus and method for correctly pronouncing proper names from text using a computer provides a dictionary which performs an initial search for the name. If the name is not in the dictionary, it is sent to a filter which either positively identifies a single language group or eliminates one or more language groups as the language group of origin for that word. When the filter cannot positively identify the language group of origin for the name, a list of possible language groups is sent to a grapheme analyzer which precedes a trigram analyzer. Using grapheme analysis, the most probable language group of origin for the name is determined and sent to a language-sensitive letter-to-sound section. In this section, the name is compared with language-sensitive rules to provide accurate phonemics and stress information for the name. The phonemics (including stress information) are sent to a voice realization unit for audio output of the name.

Abstract: A computer system has a set of memory module slots, each of which may receive a memory module or may be left empty. The memory slots are arranged to accept at least two different types of memory modules having different amounts of memory storage. Each type of memory module generates a module type signal which denotes the type of the module and thus the amount of memory storage in the module. Whenever the system is powered on or reset, the system's memory initialization software analyzes the module type signals generated by the memory modules which are installed in memory slots. Each memory module is assigned a physical address range based solely on the size of the memory module and the slot in which it is located, regardless of what other memory modules are being used. The computer system thereby determines which portions of the computer's address space will be used for primary memory. The computer system is a multitasking computer system which has a virtual memory management system.

Abstract: A method for making files compatible between different computers having different binary structures while using the same operating system by keeping all files in a standardized canonical order when they move to or from external data storage or communication means. The method includes converting all binary data accessed from a file or communications channel from the canonical order to the natural order of the host computer before using the binary data in the host computer and converting all binary data which is to be sent to a file or communications channel from the natural order of the host computer to the canonical order before sending the binary data.

Abstract: 36 Telephone interface option module circuit for interfacing an electronic device to a telephone network. Most electronic devices, for example, modems, telephone message systems and text-to-speech systems, when coupled to a telephone network must conform to specific telephone interconnect regulations. These regulations generally vary from country to country, and therefore, the electronic device generally has to be modified to conform to a specific countries telephone regulations. The option module circuit contains the country specific telephone regulations, and when plugged into the electronic device, ensures that the electronic device conforms to those regulations.