Abstract: A data buffer apparatus to interface subsystem which operate at differing or varying data timing rates utilizing a random access memory unit for data storage. Input data is clocked into an input register synchronously with an input clock. A write/read sequence generator writes the input data from the input register into the random access memory unit. The write/read sequence generator read data out of the random access memory unit into an output holding register. The data from the output holding register is clocked at an output clock rate into the output data register from which the data is transferred out of the data buffer apparatus.