Abstract: A method for connecting a track shoe to a link is disclosed. The method may include joining the track shoe and the link using electric resistance welding. A method for constructing a track assembly is also disclosed. The method may include utilizing electric resistance welding to attach a plurality of links to a plurality of track shoes. A track assembly is also disclosed. The track assembly may include a link and a track shoe attached to the link via electric resistance welding.

Abstract: A method for connecting a track shoe to a link is disclosed. The method may include joining the track shoe and the link using friction welding. A method for constructing a track assembly is also disclosed. The method may include utilizing friction welding to attach a plurality of links to a plurality of track shoes. A track assembly is also disclosed. The track assembly may include a link and a track shoe attached to the link via friction welding.

Abstract: A data word of less than or equal to 2.sup.N bits is counted for the number of binary "1's" contained therein in log.sub.2 2.sup.N =N cycles of 3 steps each in a microprocessor. As a first step the data in a first register is logically ANDed in an arithmetic logic unit (ALU) with a mask constant from a first read only memory (ROM), with a first logical product result placed in a second register. As a second step the data from the first register is logically ANDed in the ALU with the same mask constant complemented, and a second logical product result is placed in the first register. Meanwhile, the first logical product result in the second register is shifted in a shift matrix in accordance with a shift count constant obtained from a second ROM. As a third step the shifted first logical product result from the shift matrix is ADDed in the ALU with the second logical product result from the first register, and a sum result is placed in the first register as data.

Abstract: A logic clock signal generator implemented with delay lines having a plurality of taps, wherein the taps are selectively feedback coupled to the input to produce a clock signal having a plurality of selectively variable time periods.

Abstract: Apparatus for use within a virtual memory data processing system offering a way of protecting data used at one interrupt level state from unauthorized use at another interrupt level state. A virtual memory data processing system permits a computer program to specify relative (or virtual) addresses rather than physical (or real) addresses. Most practical virtual memory data processing systems utilize a Virtual Address Translator (VAT), often called a Directory Look-Aside Table (DLAT). The VAT contains a plurality of internal conversion tables which perform virtual address to real address translation. A binary code, called the Interrupt Level Code (ILC), is appended to the virtual address of entries within the plurality of internal conversion tables within the VAT to permit the VAT to translate virtual addresses to real addresses only if the present Central Processing Unit (CPU) interrupt level state corresponds to the interrupt level state denoted by the ILC within the VAT.

Abstract: A method of and an apparatus for selectively isolating digital data bus drivers from digital data busses for fault recovery and diagnostic purposes. The digital data bus drivers may be either transistor-transistor logic (TTL) or emitter coupled logic (ECL). For TTL digital data bus drivers, the input voltage (V.sub.CC) is supplied via a switching power transistor. For ECL digital data bus drivers, the ground connection (V.sub.CC1) is made via a switching power transistor. In either case, the switching power transistor is turned on and off in response to one binary bit in an isolation register coupled to the power transistor via an open collector gate or electromechanical switch. By supplying the V.sub.CC (for TTL) or V.sub.

Abstract: An apparatus for maintaining a history of instructions which have been most recently executed by a digital computer. A push-down stack is utilized for storing the contents of the program address counter, or the operand portion of the instruction register, of the computer upon the execution of every instruction and then pushing down the push-down stack whenever the last instruction executed by the digital computer was a branch type instruction. Provision may also be made for addressing the push-down stack so that the contents thereof may be reviewed in the order opposite from which it was loaded. This apparatus allows a user or diagnostic program to have access to the address of the most recently executed branch type instructions. In this way, a history of the most recently executed instructions can be maintained to aid hardware and software diagnostics.