Patents by Inventor David G. Love
David G. Love has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10679954Abstract: A method of manufacture of an integrated circuit system includes: providing a semiconductor wafer with a bond pad; attaching a detachable carrier to the semiconductor wafer, the detachable carrier including a carrier frame portion and a terminal structure; removing the carrier frame portion with the terminal structure attached to the semiconductor wafer; and forming an encapsulation encapsulating the semiconductor wafer, the bond pad, and the terminal structure.Type: GrantFiled: August 30, 2018Date of Patent: June 9, 2020Assignee: EoPLex LimitedInventors: David G. Love, Philip Eugene Rogren
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Publication number: 20180374809Abstract: A method of manufacture of an integrated circuit system includes: providing a semiconductor wafer with a bond pad; attaching a detachable carrier to the semiconductor wafer, the detachable carrier including a carrier frame portion and a terminal structure; removing the carrier frame portion with the terminal structure attached to the semiconductor wafer; and forming an encapsulation encapsulating the semiconductor wafer, the bond pad, and the terminal structure.Type: ApplicationFiled: August 30, 2018Publication date: December 27, 2018Inventors: David G. Love, Philip Eugene Rogren
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Publication number: 20160190078Abstract: A method of manufacture of an integrated circuit system includes: providing a semiconductor wafer with a bond pad; attaching a detachable carrier to the semiconductor wafer, the detachable carrier including a carrier frame portion and a terminal structure; removing the carrier frame portion with the terminal structure attached to the semiconductor wafer; and forming an encapsulation encapsulating the semiconductor wafer, the bond pad, and the terminal structure.Type: ApplicationFiled: December 21, 2015Publication date: June 30, 2016Inventors: David G. Love, Philip Eugene Rogren
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Patent number: 8116097Abstract: An apparatus for coupling an integrated circuit (IC) package to a printed circuit board. The apparatus includes an interposer an interposer having a plurality of connections suitable for surface mounting on corresponding pads of a printed circuit board (PCB). The plurality of connections is arranged in a grid array. The interposer further includes a plurality of plated through holes. The apparatus further includes a substrate having a plurality of pins. The substrate is coupled to the interposer by inserting each of the plurality of pins into a corresponding one of the plurality of plated through holes of the interposer. An IC package including an IC is mounted on the substrate.Type: GrantFiled: November 2, 2007Date of Patent: February 14, 2012Assignee: Oracle America, Inc.Inventors: David G. Love, Bidyut K. Sen
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Publication number: 20090113698Abstract: An apparatus for coupling an integrated circuit (IC) package to a printed circuit board. The apparatus includes an interposer an interposer having a plurality of connections suitable for surface mounting on corresponding pads of a printed circuit board (PCB). The plurality of connections is arranged in a grid array. The interposer further includes a plurality of plated through holes. The apparatus further includes a substrate having a plurality of pins. The substrate is coupled to the interposer by inserting each of the plurality of pins into a corresponding one of the plurality of plated through holes of the interposer. An IC package including an IC is mounted on the substrate.Type: ApplicationFiled: November 2, 2007Publication date: May 7, 2009Inventors: David G. Love, Bidyut K. Sen
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Patent number: 6317326Abstract: An integrated circuit device package is integrated with a heat dissipation member to reduce the number of junctions in a packaged integrated circuit device. For example, the integrated circuit device package may include a substrate and a thermally conductive lid coupled to a first surface of the substrate, forming a closed cavity which encloses an integrated circuit die. The thermally conductive lid may be integrated with the heat dissipation member.Type: GrantFiled: September 14, 2000Date of Patent: November 13, 2001Assignee: Sun Microsystems, Inc.Inventors: Marlin R. Vogel, David G. Love
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Patent number: 6168971Abstract: A method of assembling thin film jumper connectors to a substrate as part of a process of manufacturing a multi-chip-module or other device having multiple components bonded to chip carrier or other substrate. An alignment plate is positioned on the chuck of a standard flip-chip bonding machine. The thin film jumper connectors are placed on the alignment plate in a face-up position after alignment to alignment marks on the plate using the machine's moveable platform and split-field viewer. The jumper connectors are held to the alignment plate by a force supplied by the vacuum system of the flip-chip bonder, with the force being transmitted to the jumpers through vacuum holes in the alignment plate. The plate's alignment marks are positioned so that when they are aligned with corresponding marks on the connectors, the bonding pads on the connectors are correctly aligned to the pads on the substrate.Type: GrantFiled: May 5, 1998Date of Patent: January 2, 2001Assignee: Fujitsu LimitedInventors: David G. Love, Patricia R. Boucher, David A. Horine
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Patent number: 6126059Abstract: Disclosed are methods and apparatuses for forming solder bumps on integrated circuit chips (and other similar circuitized units) and apparatuses. A screening stencil is laid over the surface of the substrate and solder paste material is deposited into the stencil's apertures with a screening blade. The stencil is placed in such a manner that each of its apertures is positioned over a substrate pad, upon which a solder bump is to be formed. Next, a flat pressure plate is laid over the exposed top surface of the stencil, which creates a fully enclosed, or "captured", cell of solder paste within each stencil aperture. Then, with the stencil and plate remaining in place on top of the substrate, the substrate is heated to a temperature sufficient to reflow the solder paste material. After reflow, the substrate is cooled, and the pressure plate and stencil are thereafter removed, leaving solder bumps on the substrate.Type: GrantFiled: August 24, 1999Date of Patent: October 3, 2000Assignee: Fujitsu LimitedInventors: John T. MacKay, Thomas E. Molinaro, David G. Love, Patricia R. Boucher
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Patent number: 5988487Abstract: Methods for forming solder bumps on integrated circuit chips (and other similar circuitized units). A screening stencil is laid over the surface of the substrate and solder paste material is deposited into the stencil's apertures with a screening blade. The stencil is placed in such a manner that each of its apertures is positioned over a substrate pad, upon which a solder bump is to be formed. Next, a flat pressure plate is laid over the exposed top surface of the stencil, which creates a fully enclosed or "captured", cell of solder paste within each stencil aperture. Then, with the stencil and plate remaining in place on top of the substrate, the substrate is heated to a temperature sufficient to reflow the solder paste material. After reflow, the substrate is cooled, and the pressure plate and stencil are thereafter removed, leaving solder bumps on the substrate. The use of the pressure plate ensures the proper formation of the solder bumps at high densities of solder bumps (i.e.Type: GrantFiled: May 27, 1997Date of Patent: November 23, 1999Assignees: Fujitsu Limited, Semi-PacInventors: John T. MacKay, Thomas E. Molinaro, David G. Love, Patricia R. Boucher
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Patent number: 5897341Abstract: A method of interconnecting integrated circuit chips to a substrate during the assembly of a multi-chip module. Instead of forming an electrical and physical bond by reflowing solder bumps attached to the pads of the chips and the substrate, as in flip-chip bonding, thin pads of specially selected dissimilar metals placed on the chips and substrate are connected by a solid-state diffusion bonding process. In one embodiment, the I/O pads on a chip are formed from aluminum or an aluminum alloy and are aligned and placed into physical contact with corresponding metal pads or metal layered pads on a substrate, where the metal is capable of being diffusion bonded to aluminum. The combination of chip(s) and substrate are then heated in a controlled atmosphere at a temperature and for a time sufficient to cause solid-state diffusion bonding to occur.Type: GrantFiled: July 2, 1998Date of Patent: April 27, 1999Assignee: Fujitsu LimitedInventors: David G. Love, Larry L. Moresco
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Patent number: 5597412Abstract: A method and apparatus for filling small diameter, high aspect ratio via openings with a plating solution are disclosed. An apparatus according to the invention comprises a sealable chamber for receiving one or more a multichip module substrate comprising via openings to be plated. A vacuum pump is used to evacuate the chamber after the substrate(s) are positioned therein and the chamber has been sealed. Plating solution is then introduced into the chamber to immerse the substrate(s), and the solution is pressurized, forcing the liquid into the via openings. In one preferred embodiment, the chamber comprises two subchambers separated by a flexible wall. After the subchamber holding the substrate(s) has been evacuated and filled with plating solution, the other subchamber is pressurized, as with compressed air, such that a force is applied to the flexible wall creating hydrostatic pressure within the first subchamber.Type: GrantFiled: February 15, 1995Date of Patent: January 28, 1997Assignee: Fujitsu LimitedInventors: Carlo Grilletto, David G. Love
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Patent number: 5536362Abstract: Methods of constructing a wire interconnect structure on a substrate are described. The methods broadly comprise the steps of depositing a spacer layer on a surface of the substrate, depositing a mask layer on the spacer layer, and removing a first portion of the mask layer overlying a desired area on the substrate surface to expose the spacer layer underlying the first portion of the mask layer. The methods further comprise the step of etching the structure such that a first portion of the spacer layer overlaying the desired area is removed and such that a portion of the desired area is exposed, and the step of depositing a first conductive material on the exposed portion of the desired area such that a conductive post is formed on the substrate surface and mounted to the desired area. Some of the disclosed methods comprise additional steps for forming an interconnect structure on the opposite surface of the substrate and providing an electrical interconnect means between the two interconnect structures.Type: GrantFiled: February 16, 1994Date of Patent: July 16, 1996Assignee: Fujitsu LimitedInventors: David G. Love, Larry L. Moresco, William Tai-Hua Chou, David A. Horine, Connie M. Wong, Solomon I. Beilin
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Patent number: 5515604Abstract: A high-density laminated connector having a plurality of rigid dielectric layers laminated together is described. The rigid construction of the connector permits precise dimensions of the connector and, thus, accurate attachment of adjacent interconnect substrates. The dielectric layers include traces which have contact pads or bumps formed at the surfaces of the connector for connection to the traces of one or more adjacent interconnect substrates. The contact pads may comprise soft gold, solder, or various elastomeric materials. The use of soft gold contacts enables the connector to be easily removed from an adjacent interconnect substrate. In other embodiments, the rigid dielectric layers may comprise recesses where the contact pads are placed. This ensures physical alignment of the interconnect substrate and the connector, so that dimensional integrity is maintained when pressure is applied to the connector. The traces within the connector can be of a varied width, pitch, and direction.Type: GrantFiled: October 12, 1993Date of Patent: May 14, 1996Assignee: Fujitsu LimitedInventors: David A. Horine, David G. Love
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Patent number: 5514906Abstract: A compact, reliable, and efficient cooling system for semiconductor chips is disclosed. In one embodiment, a plurality of semiconductor chips have their active surfaces mounted to a major substrate which provides electrical connections among the chips, and a cooling channel is formed above the major substrate and each chip for conducting a cooling fluid over the back surface of the chips. To increase cooling efficiency, heat sink arrays are formed on the back surfaces of the chips, each array including a plurality of heat conducting elements attached to the back surface. The arrays may be readily and inexpensively constructed with photo-lithography or wire bonding techniques. To control the flow of cooling fluid around the chip edges and to prevent cavitation of the cooling fluid a cavitation and flow control plate disposed at the bottom surface of the cooling channel and formed around the edges of the chips is included.Type: GrantFiled: November 10, 1993Date of Patent: May 7, 1996Assignee: Fujitsu LimitedInventors: David G. Love, Larry L. Moresco, David A. Horine, Wen-chou V. Wang, Richard L. Wheeler, Patricia R. Boucher, Vivek Mansingh
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Patent number: 5477160Abstract: Manufacturing of semiconductor devices is facilitated when the device chip carriers of the devices are tested, prior to population of chips thereon, by a module test card. The module test card is formed by a test substrate and a plurality of test chips mounted on the test substrate. Connections are provided on the test substrate for connecting to a tester. Through the module test card, the device chip carriers are tested under simulation of their operating conditions.Type: GrantFiled: August 6, 1993Date of Patent: December 19, 1995Assignee: Fujitsu LimitedInventor: David G. Love
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Patent number: 5404265Abstract: A bypass capacitor for use with an integrated circuit module, and method of making the same, are shown. The integrated circuit module comprises an integrated circuit "chip" mounted in opposing relationship to a carrier substrate and having a plurality of interconnects, such as solder bumps or wire interconnects, for providing signal lines and supplying power to the chip. Some of the interconnects are, instead, used to form capacitors such that bypass capitance is placed in close proximity to the chip, while not using up valuable real estate on the chip or on the carrier substrate. Various embodiments of such bypass capacitors are shown.Type: GrantFiled: August 28, 1992Date of Patent: April 4, 1995Assignee: Fujitsu LimitedInventors: Larry L. Moresco, David G. Love, Wen-Chou V. Wang
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Patent number: 5363038Abstract: Manufacturing of semiconductor devices is facilitated when the device chip carriers of the devices are tested, prior to population of chips thereon, by a module test card. The module test card is formed by a test substrate and a plurality of test chips mounted on the test substrate. Connections are provided on the test substrate for connecting to a tester. Through the module test card, the device chip carriers are tested under simulation of their operating conditions.Type: GrantFiled: August 12, 1992Date of Patent: November 8, 1994Assignee: Fujitsu LimitedInventor: David G. Love
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Patent number: 5334804Abstract: An interconnect structure for connecting an integrated circuit (IC) chip to a supporting substrate is described. The supporting substrate serves to communicate signals between the IC chip and the "outside world," such as other IC chips. In one embodiment, the interconnect structure comprises an interconnect substrate having a first post disposed on one of its surfaces and a second post disposed on another of its surfaces. One post is for contacting the IC chip and the other is for contacting the major substrate. Each post comprises an elongated body having top and bottom ends, with the bottom end being mounted to one of the substrate surfaces and the top end having a substantially flat surface which is substantially co-planer with the substrate surface. The interconnect substrate further comprises a device for de-concentrating the mechanical stain present at one or both of the top and bottom ends of each post.Type: GrantFiled: November 17, 1992Date of Patent: August 2, 1994Assignee: Fujitsu LimitedInventors: David G. Love, Larry L. Moresco, William T. Chou, David A. Horine, Connie M. Wong, Solomon I. Beilin