Abstract: The present invention relates to a method and system for reducing integral non linearity errors in a pipeline Analog to Digital Converter (ADC). The invention provides in a first embodiment a method comprising the steps of: adding an analog dither signal to the analog input signal of a pipeline Analog to Digital Converter, and converting the analog input signal to a digital output signal by means of the pipeline Analog to Digital Converter. The amplitude of the analog dither signal is determined by the architecture of the Analog to Digital Converter. The invention also provides in a second embodiment a circuit comprising a pipeline analog to digital converter for converting an analog input signal to a digital output signal and a feedback circuit coupled to the converter such that the digital output signal is adapted to have an average non linearity error value of about zero LSBs.

Abstract: A multi-channel analog-to-digital converter system includes an array of sub-analog-to-digital converters wherein within the array of sub-analog-to-digital converters, there is at least one designated reference analog-to-digital converter. The analog-to-digital converter system also includes a non-sequential channel select circuit to control a selection of the analog-to-digital converters and the reference analog-to-digital converter to non-sequentially interleave the outputs of said analog-to-digital converters and said reference analog-to-digital converter. Each channel of the plurality of sub-analog-to-digital converters includes a timing skew estimation circuit. Each timing skew estimation circuit receives an output signal from the reference analog-to-digital converter and receives the output signal from the associated analog-to-digital converter.

Abstract: A comparator includes a circuit which provides a plurality of common-mode difference signals in response to differential input signals. The circuit provides a common-mode feedback signal in response to the plurality of common-mode difference signals. The common-mode feedback signal is used to drive the common-mode level of an amplifier to a desired value.

Abstract: Methods and controllers are provided to estimate and reduce phase errors between converters of time-interleaved analog-to-digital systems by generating corresponding error signals in the form of difference signals. The difference signals concern differences between magnitudes of first adjacent samples and interleaved second adjacent samples of the converters. The difference signals can be applied (e.g., to a converter's input sampler or to a variable delay element inserted after the converter) to substantially reduce the phase errors. The methods and controllers may be economically implemented because they can be realized with simple operations (e.g., addition and subtraction). Although some embodiments are facilitated with knowledge of parameters of the analog input signal, others do not require this knowledge so long as the signal is restricted to lie within a single Nyquist zone.

Abstract: A circuit with a common-mode dual output includes a feedback circuit connected to alternate the states of the dual output between an average output level and a desired common-mode level. The difference between the average and desired levels is proportional to a signal offset level. An impedance matching circuit is connected to the feedback circuit to adjust the signal offset level.

Abstract: Timing enhancements of embodiments of the invention are realized in time-interleaved converter systems with minimal network additions that facilitate the insertion of a timing signal into the system's input analog signal. The timing signal travels with the input analog signal so that it continues to accurately define predetermined sample times in the analog signal even as they travel over different path lengths to individual converters. Each converter has a feedback path which adjusts the timing of that converter's samples with a correction signal whose value is determined by contributions of first and second different amplitudes of the timing signal to that converter's output signals.

Abstract: A signal conditioning system includes first and second converters coupled to a random clock which provides a random sampling rate. Corresponding offset sensor coupled with the first and second converters sense and adjust an offset signal difference. A gain sensor is coupled with the first and second converters to sense a gain difference between the first and second converters and a gain corrector is coupled with the gain sensor to adjust the gain difference.

Abstract: A sample and hold circuit having a semiconductor with a field effect transistor therein. The field effect transistor has a channel in the semiconductor, a source region in the semiconductor, a drain region in the semiconductor a front-gate disposed over the channel, and a back-gate in the semiconductor under the channel. The front-gate and back-gate are configured to control a flow of carriers in the semiconductor through a length of the channel between the source region and the drain region. A capacitor is connected to one of the drain and source regions. The other one of the source and drain region is configured for coupling to an input signal. A switch is responsive to a sampling signal to electrically connect a constant electrical potential between one of the source and drain regions and back-gate during a tracking phase. In one embodiment, the sample and hold circuit includes a second switch to electrically a second constant potential between the front-gate and one of the source and drain.