Abstract: A successive approximation circuit and method are disclosed for digitally approximating a moving signal using an analog-digital converter (ADC) and a comparator for generating a comparison signal from the moving signal. An estimate register and a bit and conversion control circuit are provided, with the bit and conversion control circuit including a bit control circuit and a conversion control circuit, where the bit control circuit adjusts a current plurality of output bits to compensate for an error due to a slew rate to generate the digitally approximated moving signal. An adder is included for adding the control value to the current plurality of output bits to generate the next plurality of output bits. Alternatively, an adjustment selection circuit and a logic chain circuit are included.

Abstract: The offset associated with mismatch of a pair of input devices in comparators used in applications such as flash converters is eliminated by using only one input device or transconductance circuit, time-shared between the input and reference signals. The input device converts each signal in succession into a current. A current copier stores one of these currents while the input device produces the other current, and the two currents are then compared by connecting them to a common node. The comparator includes a first switch for switching between an input and reference nodes, and an input device which receives a reference signal from the reference node during a first comparison cycle, receives an input signal from the input node during a second comparison cycle, and converts the input signal and the reference signal to input and reference currents, respectively.