Patents by Inventor David Gaied

David Gaied has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Capacitance bank systems and methods
    Patent number: 9390861
    Abstract: A capacitance bank system includes a plurality of voltage controlled capacitance cells and an output node. The plurality of capacitance cells have an anti-parallel configuration. The plurality of capacitance cells are configured to selectively provide cell capacitances. The output node is coupled to the plurality of capacitance cells. The output node is configured to provide an input capacitance step smaller than a minimum physical capacitor supported by a particular technology.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: July 12, 2016
    Assignee: Intel Deutschland GmbH
    Inventors: David Gaied, Ahmed Nader Mohieldin
  • Low power oscillator with negative resistance boosting
    Patent number: 8957740
    Abstract: Representative implementations of devices and techniques provide increased negative resistance to an oscillator circuit. A capacitance divider and/or a feedback loop may be employed to increase the negative resistance of the oscillator circuit at the same current consumption and with the same load capacitance. Further, a constant bias circuit may be employed to conserve and/or reduce the current consumption of the oscillator circuit.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 17, 2015
    Assignee: Intel Mobile Communications GmbH
    Inventors: David Gaied, Emad Hegazi, Karim Hussein
  • LOW POWER OSCILLATOR WITH NEGATIVE RESISTANCE BOOSTING
    Publication number: 20140266478
    Abstract: Representative implementations of devices and techniques provide increased negative resistance to an oscillator circuit. A capacitance divider and/or a feedback loop may be employed to increase the negative resistance of the oscillator circuit at the same current consumption and with the same load capacitance. Further, a constant bias circuit may be employed to conserve and/or reduce the current consumption of the oscillator circuit.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Inventors: David GAIED, Emad HEGAZI, Karim HUSSEIN
  • Capacitance Bank Systems and Methods
    Publication number: 20140210278
    Abstract: A capacitance bank system includes a plurality of voltage controlled capacitance cells and an output node. The plurality of capacitance cells have an anti-parallel configuration. The plurality of capacitance cells are configured to selectively provide cell capacitances. The output node is coupled to the plurality of capacitance cells. The output node is configured to provide an input capacitance step smaller than a minimum physical capacitor supported by a particular technology.
    Type: Application
    Filed: January 29, 2013
    Publication date: July 31, 2014
    Inventors: David Gaied, Ahmed Nader Mohieldin