Abstract: Track and trace packaging is disclosed which may also be damage indicating. Track and trace functionality may be incorporated on, in or near the packaging at various stages of a supply chain. A damage indicating material can be incorporated into a variety of packaging substrates, which may change color when exposed to oxygen, excessive heat and/or excessive pressure. An anti-counterfeiting taggant material may be used to provide track and trace capabilities. Exemplary products with which the present track and trace packaging may be used include packaged condoms, food and beverages, pharmaceuticals, cannabis and the like.

Abstract: A method and apparatus for imaging seismic data includes obtaining an initial model of a subsurface formation, wherein the model includes a plurality of nodes that form at least part of a grid; an initial dip value for the nodes; and a set of origin coordinates for each of the nodes; performing bottom-up ray tracing for each node in the model, resulting in a set of arrival coordinates for each node; identifying a plurality of gathers from the seismic data; for each gather: calculating a set of midpoint coordinates; defining a midpoint vicinity surrounding the set of midpoint coordinates; identifying the nodes having arrival coordinates within the midpoint vicinity; and estimating a unique aperture for each of the gathers based on the respective origin coordinates; storing the estimated apertures in a table; and generating a subsurface volume or image with subsurface reflectors determined with apertures of the respective gathers.

Abstract: A method and apparatus for imaging seismic data includes obtaining an initial model of a subsurface formation, wherein the model includes a plurality of nodes that form at least part of a grid; an initial dip value for the nodes; and a set of origin coordinates for each of the nodes; performing bottom-up ray tracing for each node in the model, resulting in a set of arrival coordinates for each node; identifying a plurality of gathers from the seismic data; for each gather: calculating a set of midpoint coordinates; defining a midpoint vicinity surrounding the set of midpoint coordinates; identifying the nodes having arrival coordinates within the midpoint vicinity; and estimating a unique aperture for each of the gathers based on the respective origin coordinates; storing the estimated apertures in a table; and generating a subsurface volume or image with subsurface reflectors determined with apertures of the respective gathers.

Abstract: Track and trace packaging is disclosed which may also be damage indicating. Track and trace functionality may be incorporated on, in or near the packaging at various stages of a supply chain. A damage indicating material can be incorporated into a variety of packaging substrates, which may change color when exposed to oxygen, excessive heat and/or excessive pressure. An anti-counterfeiting taggant material may be used to provide track and trace capabilities. Exemplary products with which the present track and trace packaging may be used include packaged condoms, food and beverages, pharmaceuticals, cannabis and the like.

Abstract: Damage indicating packaging is disclosed. A damage indicating material may be applied between inner and outer wrapper layers. When the damage indicating material is exposed to oxygen, excessive heat and/or excessive pressure, the material changes in appearance to thereby alert the user that the package may be compromised. The damage indicating material may include an anti-counterfeiting taggant material. Active and intelligent tamper-evident packaging is thus provided.

Abstract: Damage indicating packaging is disclosed. A damage indicating material may be applied between inner and outer wrapper layers. When the damage indicating material is exposed to oxygen, excessive heat and/or excessive pressure, the material changes in appearance to thereby alert the user that the package may be compromised. The damage indicating material may include an anti-counterfeiting taggant material. Active and intelligent tamper-evident packaging is thus provided.

Abstract: Systems and methods for performing semiconductor laser annealing using dual loop control are disclosed. The first control loop operates at a first frequency and controls the output of the laser and controls the 1/f laser noise. The second control loop also controls the amount of output power in the laser and operates at second frequency lower than the first frequency. The second control loop measures the thermal emission of the wafer over an area the size of one or more die so that within-die emissivity variations are average out when determining the measured annealing temperature. The measured annealing temperature and an annealing temperature set point are used to generate the control signal for the second control loop.

Abstract: Damage indicating packaging is disclosed. A damage indicating material may be applied between inner and outer wrapper layers. When the damage indicating material is exposed to oxygen, excessive heat and/or excessive pressure, the material changes in appearance to thereby alert the user that the package may be compromised. The damage indicating material may include an anti-counterfeiting taggant material. Active and intelligent tamper-evident packaging is thus provided.

Abstract: Systems and methods for measuring an intensity characteristic of a light beam are disclosed. The methods include directing the light beam into a prism assembly that includes a thin prism sandwiched by two transparent plates, and reflecting a portion of the light beam by total-internal-reflection surface to an integrating sphere while transmitting the remaining portion of the light beam through the two transparent plates to a beam dump. The method also includes detecting light captured by the integrating sphere and determining the intensity characteristic from the detected light.

Abstract: Systems and methods for measuring an intensity characteristic of a light beam are disclosed. The methods include directing the light beam into a prism assembly that includes a thin prism sandwiched by two transparent plates, and reflecting a portion of the light beam by total-internal-reflection surface to an integrating sphere while transmitting the remaining portion of the light beam through the two transparent plates to a beam dump. The method also includes detecting light captured by the integrating sphere and determining the intensity characteristic from the detected light.

Abstract: Damage evident condom packaging is disclosed. A damage indicating material may be applied between inner and outer wrapper layers. When the damage indicating material is exposed to oxygen, excessive heat and/or excessive pressure, the material changes in appearance to thereby alert the user that the condom package may be compromised. Active and intelligent tamper-evident condom packaging is thus provided.

Abstract: Systems and methods for performing semiconductor laser annealing using dual loop control are disclosed. The first control loop operates at a first frequency and controls the output of the laser and controls the 1/f laser noise. The second control loop also controls the amount of output power in the laser and operates at second frequency lower than the first frequency. The second control loop measures the thermal emission of the wafer over an area the size of one or more die so that within-die emissivity variations are average out when determining the measured annealing temperature. The measured annealing temperature and an annealing temperature set point are used to generate the control signal for the second control loop.

Abstract: Systems and methods for performing semiconductor laser annealing using dual loop control are disclosed. The first control loop operates at a first frequency and controls the output of the laser and controls the 1/f laser noise. The second control loop also controls the amount of output power in the laser and operates at second frequency lower than the first frequency. The second control loop measures the thermal emission of the wafer over an area the size of one or more die so that within-die emissivity variations are average out when determining the measured annealing temperature. The measured annealing temperature and an annealing temperature set point are used to generate the control signal for the second control loop.

Abstract: A behavioral synthesis tool for generating an integrated circuit design is described. The behavioral synthesis tool allows a designer to interactively allocate loop configuration information without having to modify a source code description of the integrated circuit. The behavioral synthesis tool reads the source code description and generates a synthesis intermediate format stored in memory. The synthesis tool searches the in-memory synthesis intermediate format to find loops. The loops are then listed in a graphical user interface (GUI) in hierarchical fashion. The GUI also lists loop configuration information associated with the loops, such as loop frequency, loop unrolling and loop pipelining. The GUI allows the designer to modify the loop configuration information without having to update the source code description.

Abstract: A behavioral synthesis tool for generating an integrated circuit design is described. The behavioral synthesis tool allows a designer to interactively allocate loop configuration information without having to modify a source code description of the integrated circuit. The behavioral synthesis tool reads the source code description and generates a synthesis intermediate format stored in memory. The synthesis tool searches the in-memory synthesis intermediate format to find loops. The loops are then listed in a graphical user interface (GUI) in hierarchical fashion. The GUI also lists loop configuration information associated with the loops, such as loop frequency, loop unrolling and loop pipelining. The GUI allows the designer to modify the loop configuration information without having to update the source code description.

Abstract: A behavioral synthesis tool for generating an integrated circuit design is described. The behavioral synthesis tool allows a designer to interactively allocate loop configuration information without having to modify a source code description of the integrated circuit. The behavioral synthesis tool reads the source code description and generates a synthesis intermediate format stored in memory. The synthesis tool searches the in-memory synthesis intermediate format to find loops. The loops are then listed in a graphical user interface (GUI) in hierarchical fashion. The GUI also lists loop configuration information associated with the loops, such as loop frequency, loop unrolling and loop pipelining. The GUI allows the designer to modify the loop configuration information without having to update the source code description.

Abstract: A tool is disclosed that allows a hardware designer using a behavioral synthesis tool to view a calculated execution time for a group of related loops identified in source code describing a hardware design circuit. Further, a designer can then interactively unroll and/or pipeline a selected loop without having to modify the source code description of the circuit. Using a graphical user interface (GUI), the designer can modify the loop design easily and see the results of the new loop configuration without having to generate the RTL code, perform RTL synthesis, etc. For example, the designer can readily view the relative loop execution time of the circuit to better determine whether the design is acceptable. Additionally, the designer can execute an area-versus-latency analysis, and, if the analysis is not satisfactory, the designer can unroll and or pipeline selected loops using the GUI.

Abstract: A behavioral synthesis tool for generating an integrated circuit design is described. The behavioral synthesis tool allows a designer to interactively allocate loop configuration information without having to modify a source code description of the integrated circuit. The behavioral synthesis tool reads the source code description and generates a synthesis intermediate format stored in memory. The synthesis tool searches the in-memory synthesis intermediate format to find loops. The loops are then listed in a graphical user interface (GUI) in hierarchical fashion. The GUI also lists loop configuration information associated with the loops, such as loop frequency, loop unrolling and loop pipelining. The GUI allows the designer to modify the loop configuration information without having to update the source code description.

Abstract: A behavioral synthesis tool for generating an integrated circuit design is described. The behavioral synthesis tool allows a designer to interactively allocate variables or arrays to memory resources without having to modify a source code description of the integrated circuit. The behavioral synthesis tool reads the source code description and generates a synthesis intermediate format stored in memory. The synthesis tool searches the in-memory synthesis intermediate format to find arrays for each process. The arrays are then listed in a graphical user interface (GUI). The GUI allows the designer to create memory resources, specifying the type of memory, the packing mode, etc. The designer can then drag and drop the array variables listed in the GUI onto the memory resources. Upon completion of modifying the memory allocation, the designer saves the changes illustrated in the GUI and such changes are effectuated by automatically updating the synthesis intermediate format.

Abstract: A tool is disclosed that allows a hardware designer using a behavioral synthesis tool to view a calculated execution time for a group of related loops identified in source code describing a hardware design circuit. Further, a designer can then interactively unroll and/or pipeline a selected loop without having to modify the source code description of the circuit. Using a graphical user interface (GUI), the designer can modify the loop design easily and see the results of the new loop configuration without having to generate the RTL code, perform RTL synthesis, etc. For example, the designer can readily view the relative loop execution time of the circuit to better determine whether the design is acceptable. Additionally, the designer can execute an area-versus-latency analysis, and, if the analysis is not satisfactory, the designer can unroll and or pipeline selected loops using the GUI.