Abstract: A microprocessor has RAS and CAS outputs for exclusive coupling, via a bus, to RAS and CAS inputs of a private DRAM. The microprocessor has a DRAM Control Register having at least one bit which is set to designate whether the DRAM is private to the microprocessor, a read circuit which reads the one bit and determines whether the bit is set, and a control logic circuit coupled to the read circuit for controlling functions of the microprocessor according to whether the DRAM is private to it.

Abstract: A method and apparatus are provided for inserting an address at the beginning of a data stream that is being transferred through a FIFO buffer (65). The address is inserted at the beginning of the data stream to prevent the address from being lost. An address decoder (102) is used to identify a range of addresses that can access the FIFO buffer (65). The address may also contain header information for determining the destination of the data stream in a data processing system (20), and also contain information for controlling how the data stream is to be processed in the data processing system (20).

Abstract: Subsystems (12-20) are coupled by a bus (44) which includes higher order address lines (62, 64) and lower order address lines (60). One or more subsystems (20) has an address connection (202) for receiving lower order addresses (76') identifying an address space (INT) within this subsystem (20). This connection (202) is coupled to the higher order address lines (62, 64) of the bus (44). An address generator (22) provides subsystem select (CS) addresses and lower order (INT) addresses. A control means (24) coupled between the address generator (22) and the bus (44), uses the subsystem select (CS) addresses to dynamically couple the lower order (INT) addresses from the address generator (22) to the higher order bus lines (62, 64) when the subsystem select (CS) address is for the chosen subsystem (20). This reduces the number of subsystems (12-20) coupled to the lower order bus lines (60) and helps equalize bus (44) loading.

Abstract: An adjustable depth/width FIFO buffer (65) is provided that accommodates variable width data transfers. The FIFO buffer (65) has two sections of read/write registers (73, 75) that are each independently controlled for transferring 16 bit words or 32 bit words without wasting register space in the FIFO buffer (65) when transferring 16 bit words. When the FIFO buffer (65) is narrowed to transfer 16 bit words, the storage space is deepened. This allows maximum use of the FIFO buffer registers (72) when interfacing either 16 bits of parallel data or 32 bits of parallel data. The FIFO buffer (65) is a slave only buffer to a host processor, therefore, the FIFO buffer (65) cannot initiate output of data, keeping the design simple and small.

Abstract: In a data arithmetic logic unit (54), power consumption is reduced by eliminating unnecessary write backs to the destination register (82) following a MAC (multiply/accumulate) operation. A series of instructions provided to the data ALU (arithmetic/logic) (54) are monitored by a control circuit (89). When two or more consecutive instructions having identical destinations for a result are detected, the result is written to a pipeline register (78) instead of to the destination register (82) named in the consecutive instructions. Thus, only a short, lightly loaded bus to the pipeline register (78) is driven, instead of the longer heavily loaded bus to the destination register (82).