Patents by Inventor David Gammie

David Gammie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11996815
    Abstract: Disclosed examples include an apparatus. The apparatus may include a differential signal path portion, a first circuit, and a second circuit. The first circuit may be arranged at the differential signal path portion to set a differential impedance of the differential signal path portion. The second circuit may be arranged outside of the differential signal path portion to set a common-mode impedance of the differential signal path portion lower than the differential impedance.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: May 28, 2024
    Assignee: Microchip Technology Incorporated
    Inventors: Steven Vida, David Gammie
  • Publication number: 20220376666
    Abstract: One or more examples relate to an apparatus to amplify differential voltage signal components of voltage across a resistor. Such an apparatus may include a resistor; a differential amplification circuit operatively coupled with the resistor to amplify a differential voltage signal component of a voltage across the resistor; and an operative coupling between the resistor and the differential amplification circuit to pass the differential voltage signal component and isolate a common mode voltage signal component of the voltage across the resistor.
    Type: Application
    Filed: May 24, 2022
    Publication date: November 24, 2022
    Inventor: David Gammie
  • Publication number: 20220166411
    Abstract: Disclosed examples include an apparatus. The apparatus may include a differential signal path portion, a first circuit, and a second circuit. The first circuit may be arranged at the differential signal path portion to set a differential impedance of the differential signal path portion. The second circuit may be arranged outside of the differential signal path portion to set a common-mode impedance of the differential signal path portion lower than the differential impedance.
    Type: Application
    Filed: November 24, 2021
    Publication date: May 26, 2022
    Inventors: Steven Vida, David Gammie
  • Patent number: 10199919
    Abstract: A circuit and method for controlling a power converter having a high-side and a low-side switch are provided. The circuit may include a comparator configured to receive a reference voltage at a first input and a ramp voltage at a second output, and to output a delay signal based on a comparison of the reference voltage and the ramp voltage. The delay signal may be configured to turn on one or more of the high-side switch and the low-side switch. The circuit may increase or decrease the reference voltage based on a dead time, which equals an amount of time when the high-side switch and the low-side switch are turned off. The circuit may include a first switch that is controlled to lower the reference voltage if a dead time exceeds a first threshold, and a second switch that is controlled to raise the reference voltage if the dead time delay signal is below a second threshold.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: February 5, 2019
    Assignee: Microchip Technology Inc.
    Inventor: David Gammie
  • Publication number: 20180323696
    Abstract: A circuit and method for controlling a power converter having a high-side and a low-side switch are provided. The circuit may include a comparator configured to receive a reference voltage at a first input and a ramp voltage at a second output, and to output a delay signal based on a comparison of the reference voltage and the ramp voltage. The delay signal may be configured to turn on one or more of the high-side switch and the low-side switch. The circuit may increase or decrease the reference voltage based on a dead time, which equals an amount of time when the high-side switch and the low-side switch are turned off. The circuit may include a first switch that is controlled to lower the reference voltage if a dead time exceeds a first threshold, and a second switch that is controlled to raise the reference voltage if the dead time delay signal is below a second threshold.
    Type: Application
    Filed: April 24, 2018
    Publication date: November 8, 2018
    Applicant: Microchip Technology Incorporated
    Inventor: David Gammie
  • Patent number: 9837450
    Abstract: A method of operating a device comprising: a first conductor layer defining a plurality of source conductors each associated with a respective group of transistors, and a plurality of drain conductors each associated with a respective transistor; a semiconductor layer defining semiconductor channels between said source and drain conductors; a second conductor layer defining a plurality of gate conductors each associated with a respective set of transistors, and one or more storage capacitor conductors capacitively coupled to the drain conductors for a respective set of transistors; the method comprising: using the gate conductors to switch the transistors between on and off states; and using the storage capacitor conductors to reduce the conductivity of one or more semiconductor layer connecting the drain conductor of each transistor in the on state to source and/or drain conductors other than those associated with that transistor.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: December 5, 2017
    Assignee: FLEXENABLE LIMITED
    Inventors: Stephan Riedel, David Gammie, Boon Hean Pui
  • Patent number: 9805668
    Abstract: We describe a method of reducing artefacts in an image displayed by an active matrix electro-optic display and display driver, the electro-optic display driver comprising a plurality of active matrix pixel drivers each driving a respective pixel of the electro-optic display, each active matrix pixel driver having an associated storage capacitor coupled to a common backplane connection of the display driver, pixels of the electro-optic display having a common pixel electrode, the method comprising: driving the electro-optic display with a null frame during a power-down procedure of the display.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: October 31, 2017
    Assignee: FLEXENABLE LIMITED
    Inventors: Tiziano Agostinelli, Jeremy Hills, David Gammie, Stephan Riedel, Boon Hean Pui
  • Publication number: 20160233254
    Abstract: A method of operating a device comprising: a first conductor layer defining a plurality of source conductors each associated with a respective group of transistors, and a plurality of drain conductors each associated with a respective transistor; a semiconductor layer defining semiconductor channels between said source and drain conductors; a second conductor layer defining a plurality of gate conductors each associated with a respective set of transistors, and one or more storage capacitor conductors capacitively coupled to the drain conductors for a respective set of transistors; the method comprising: using the gate conductors to switch the transistors between on and off states; and using the storage capacitor conductors to reduce the conductivity of one or more semiconductor layer connecting the drain conductor of each transistor in the on state to source and/or drain conductors other than those associated with that transistor.
    Type: Application
    Filed: October 7, 2014
    Publication date: August 11, 2016
    Applicant: FLEXENABLE LIMITED
    Inventors: Stephan RIEDEL, David GAMMIE, Boon Hean PUI
  • Publication number: 20150161946
    Abstract: We describe a method of reducing artefacts in an image displayed by an active matrix electro-optic display and display driver, the electro-optic display driver comprising a plurality of active matrix pixel drivers each driving a respective pixel of the electro-optic display, each active matrix pixel driver having an associated storage capacitor coupled to a common backplane connection of the display driver, pixels of the electro-optic display having a common pixel electrode, the method comprising: driving the electro-optic display with a null frame during a power-down procedure of the display.
    Type: Application
    Filed: July 8, 2013
    Publication date: June 11, 2015
    Inventors: Tiziano Agostinelli, Jeremy Hills, David Gammie, Stephen Riedel, Boon Hean Pui
  • Patent number: 7239204
    Abstract: An amplifier circuit includes first (7A) and second (7B) operational amplifiers connected in a parallel configuration. A first terminal (12) of a first input resistor (5) is coupled to one input of both of the first (7A) and second (7B) amplifiers. A first terminal (15) of a second input resistor (6) is coupled to another input of both of the first (7A) and second (7B) amplifiers. A differential input voltage is applied between the second terminals of the first and second input resistors. The output signals of the first (7A) and second (7B) operational amplifiers are combined to produce an output signal (11AB) representative of feedback currents produced in the first (5) and second (6) input resistors. Upper and lower common mode input voltage ranges associated with the differential input voltage extend substantially above and below the upper and lower supply voltages, respectively, of the amplifier circuit.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: July 3, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: David A. Gammie, Edward Mullins, Jeffery B. Parfenchuck
  • Patent number: 7196581
    Abstract: An amplifier circuit includes first (7A) and second (7B) operational amplifiers connected in a generally parallel configuration, each with inputs coupled through the same pair of matched input resistors which receive a differential input signal that may have both a positive and negative common mode range. An offset adjustment amplifier (17) receives a differential error signal representative of the difference between offset voltages of the first and second operational amplifiers and generates offset adjustment signals that are applied to input stages of the first and second operational amplifiers to adjust their respective offset voltages so as to equalize them.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: March 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: David A. Gammie, Sergey V. Alenin
  • Publication number: 20060267687
    Abstract: An amplifier circuit includes first (7A) and second (7B) operational amplifiers connected in a parallel configuration. A first terminal (12) of a first input resistor (5) is coupled to one input of both of the first (7A) and second (7B) amplifiers. A first terminal (15) of a second input resistor (6) is coupled to another input of both of the first (7A) and second (7B) amplifiers. A differential input voltage is applied between the second terminals of the first and second input resistors. The output signals of the first (7A) and second (7B) operational amplifiers are combined to produce an output signal (11AB) representative of feedback currents produced in the first (5) and second (6) input resistors. Upper and lower common mode input voltage ranges associated with the differential input voltage extend substantially above and below the upper and lower supply voltages, respectively, of the amplifier circuit.
    Type: Application
    Filed: May 24, 2005
    Publication date: November 30, 2006
    Inventors: David Gammie, Edward Mullins, Jeffery Parfenchuck
  • Publication number: 20060261884
    Abstract: An amplifier circuit includes first (7A) and second (7B) operational amplifiers connected in a generally parallel configuration, each with inputs coupled through the same pair of matched input resistors which receive a differential input signal that may have both a positive and negative common mode range. An offset adjustment amplifier (17) receives a differential error signal representative of the difference between offset voltages of the first and second operational amplifiers and generates offset adjustment signals that are applied to input stages of the first and second operational amplifiers to adjust their respective offset voltages so as to equalize them.
    Type: Application
    Filed: May 20, 2005
    Publication date: November 23, 2006
    Inventors: David Gammie, Sergey Alenin
  • Patent number: 6801075
    Abstract: A base current compensation circuit is configured for injecting base current to the base of a transistor device to compensate for the lost current demanded by a transistor base. The base current compensation circuit is configured to inject current into the base of the transistor without the headroom requirements, as well as being less complex than other approaches. An exemplary base current compensation circuit comprises a sampling circuit and a current mirror feedback circuit configured for providing multiples of the base current demanded by the transistor device.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: October 5, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: David A. Gammie, Jeffery B. Parfenchuck, Jerry L. Doorenbos
  • Patent number: 6667650
    Abstract: A leakage compensation circuit and technique is provided that compensates for losses in a referenced current of an amplifier circuit due to leakage elements. The leakage compensation circuit is configured to inject current substantially equal in magnitude to the leakage current into one or more junctions of the amplifier circuit to compensate for lost referenced current due to leakage. As a result, the amplifier circuit and various devices can realize the flow of the reference current as substantially intended without detrimental effects of leakage current, thus maintaining the integrity of the referenced current. The leakage compensation circuit comprises an array of compensation regions configured to approximate the collective loss that is created by the leakage elements and provide a compensation current substantially equal in magnitude to one or more junctions to compensate for lost referenced current.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: December 23, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: David A. Gammie, Jeffrey B. Parfenchuck, David M. Jones, Jerry L. Doorenbos
  • Publication number: 20030189459
    Abstract: A base current compensation circuit is configured for injecting base current to the base of a transistor device to compensate for the lost current demanded by a transistor base. The base current compensation circuit is configured to inject current into the base of the transistor without the headroom requirements, as well as being less complex than other approaches. An exemplary base current compensation circuit comprises a sampling circuit and a current mirror feedback circuit configured for providing multiples of the base current demanded by the transistor device.
    Type: Application
    Filed: October 2, 2002
    Publication date: October 9, 2003
    Applicant: Texas Instruments Incorporated
    Inventors: David A. Gammie, Jeffery B. Parfenchuck, Jerry L. Doorenbos
  • Publication number: 20030184359
    Abstract: A leakage compensation circuit and technique is provided that compensates for losses in a referenced current of an amplifier circuit due to leakage elements. The leakage compensation circuit is configured to inject current substantially equal in magnitude to the leakage current into one or more junctions of the amplifier circuit to compensate for lost referenced current due to leakage. As a result, the amplifier circuit and various devices can realize the flow of the reference current as substantially intended without detrimental effects of leakage current, thus maintaining the integrity of the referenced current. The leakage compensation circuit comprises an array of compensation regions configured to approximate the collective loss that is created by the leakage elements and provide a compensation current substantially equal in magnitude to one or more junctions to compensate for lost referenced current.
    Type: Application
    Filed: October 8, 2002
    Publication date: October 2, 2003
    Applicant: Texas Instruments Incorporated
    Inventors: David A. Gammie, Jeffrey B. Parfenchuck, David M. Jones, Jerry L. Doorenbos