Abstract: The present invention include a recombinant BMYV P0 viral nucleotide sequence, which when transcribed in a cell, is capable of forming a double stranded self-complementary RNA sequence. The invention is related to a method for conveying viral resistance or tolerance to one or more virus(es), in particular to beet mild yellowing virus (BMYV) and to beet necrotic yellow vein virus (BNYVV) or to BMYV alone in a plant, in particular in a sugar beet plant. Furthermore, the present invention relates to the virus-resistant or -tolerant plant obtained according to this method, as well as to seeds and progeny derived therefrom.

Abstract: A recombinant BMYV P0 viral nucleotide sequence when transcribed in a cell is capable of forming a double stranded self-complementary RNA sequence.

Abstract: The present invention is related to a method for conveying viral resistance or tolerance to one or more virus(es), in particular to beet mild yellowing virus (BMYV) and to beet necrotic yellow vein virus (BNYVV) or to BMYV alone in a plant, in particular in a sugar beet plant. Furthermore, the present invention relates to the virus resistant or -tolerant plant obtained according to this method, as well as to seeds and progeny derived therefrom.

Abstract: A recombinant BMYV P0 viral nucleotide sequence when transcribed in a cell is capable of forming a double stranded self-complementary RNA sequence.

Abstract: Capacitors, systems, and methods are disclosed. In one embodiment, the capacitor includes a first electrode. The capacitor may also include a first insulator layer having a positive VCC adjacent to the first electrode. The capacitor may further include a second insulator layer having a negative VCC adjacent to the first insulator layer. The capacitor may also include a third insulator layer having a positive VCC adjacent to the second insulator layer. The capacitor may also include a second electrode adjacent to the third insulator layer.

Abstract: Capacitors, systems, and methods are disclosed. In one embodiment, the capacitor includes a first electrode. The capacitor may also include a first insulator layer having a positive VCC adjacent to the first electrode. The capacitor may further include a second insulator layer having a negative VCC adjacent to the first insulator layer. The capacitor may also include a third insulator layer having a positive VCC adjacent to the second insulator layer. The capacitor may also include a second electrode adjacent to the third insulator layer.

Abstract: The present invention concerns a method of genetic modification of a TGB-3 wild type viral sequence for reducing or suppressing the possible deleterious effects of the agronomic properties of a transformed plant or plant cell by said TGB-3 viral sequence. The invention further relates to genetically modified TGB-3 viral sequences suitable to induce gene silencing. In particular hairpin constructs based on such sequences proved highly efficient to induce a PTGS mechanism and degradation of the whole of RNA2 thereby. When plants are transformed accordingly the spread of the virus in the plant is significantly reduced or blocked.

Abstract: The present invention concerns a method of genetic modification of a TGB-3 wild type viral sequence for reducing or suppressing the possible deleterious effects of the agronomic properties of a transformed plant or plant cell by said TGB-3 viral sequence. The invention further relates to genetically modified TGB-3 viral sequences suitable to induce gene silencing. In particular hairpin constructs based on such sequences proved highly efficient to induce a PTGS mechanism and degradation of the whole of RNA2 thereby. When plants are transformed accordingly the spread of the virus in the plant is significantly reduced or blocked.

Abstract: One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the valence band for silicon. In another embodiment, the impurity can be used in an n-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the conduction band for silicon. In a particular embodiment, a boron-containing species is implanted into a metal-containing layer within the metal-containing gate electrode within a p-channel transistor, so that the metal-containing gate electrode has a work function closer to the valence band for silicon as compared to the metal-containing gate electrode without the boron-containing species.

Abstract: A method for making a semiconductor device includes providing a first substrate region and a second substrate region, wherein at least a part of the first substrate region has a first conductivity type and at least a part of the second substrate region has a second conductivity type different from the first conductivity type. The method further includes forming a dielectric layer over at least a portion of the first substrate region and at least a portion of the second substrate region. The method further includes forming a metal-containing gate layer over at least a portion of the dielectric layer overlying the first substrate region. The method further includes introducing dopants into at least a portion of the first substrate region through the metal-containing gate layer.

Abstract: A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the gate dielectric over a first (pMOS, for example) area (32) of the substrate is exposed and gate dielectric over a second (nMOS, for example) area (33) of the substrate continues to be protected by the sacrificial layer. A first gate conductor material (51) is deposited over the remaining sacrificial area and over the exposed gate dielectric. The first gate conductor material is patterned so that first gate conductor material over the second area of the substrate is etched away. The sacrificial layer over the second area prevents damage to the underlying dielectric material as the first gate conductor material is removed.

Abstract: A metal oxide is formed over a high quality oxide which has been deposited over a substrate. An anneal drives a reaction to form a metal oxysilicon nitride layer which is then used as a part of a gate stack. The novel integration scheme allows for improved scalablity of devices as well as improved leakage currents.

Abstract: One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the valence band for silicon. In another embodiment, the impurity can be used in an n-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the conduction band for silicon. In a particular embodiment, a boron-containing species is implanted into a metal-containing layer within the metal-containing gate electrode within a p-channel transistor, so that the metal-containing gate electrode has a work function closer to the valence band for silicon as compared to the metal-containing gate electrode without the boron-containing species.

Abstract: A semiconductor fabrication annealing process includes depositing a high dielectric constant gate dielectric over a substrate and annealing the gate dielectric. Annealing the gate dielectric includes exposing the gate dielectric to an inert ambient and ramping the inert ambient to an annealing temperature. A passivating gas is then introduced into the ambient while maintaining the ambient at the annealing temperature. This passivating ambient is then maintained at the annealing temperature for a specified duration. While maintaining the presence of the passivating gas in the ambient, the ambient temperature is then ramped down from the annealing temperature to a second temperature, which is preferably less than 100° C. The passivating gas is preferably hydrogen gas, deuterium gas, or a combination of the two. The annealing temperature is preferably greater than approximately 470° C.

Abstract: A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the gate dielectric over a first (pMOS, for example) area (32) of the substrate is exposed and gate dielectric over a second (nMOS, for example) area (33) of the substrate continues to be protected by the sacrificial layer. A first gate conductor material (51) is deposited over the remaining sacrificial area and over the exposed gate dielectric. The first gate conductor material is patterned so that first gate conductor material over the second area of the substrate is etched away. The sacrificial layer over the second area prevents damage to the underlying dielectric material as the first gate conductor material is removed.

Abstract: A semiconductor device and fabrication process includes forming a gate dielectric overlying a semiconductor substrate and a gate electrode overlying the gate dielectric. The gate electrode includes an interface between a first portion of the gate electrode and a second portion of the gate electrode. A silicide is then formed overlying the gate electrode. The presence of the gate electrode interface substantially prevents the silicide from spiking into or through the gate electrode to encroach upon or contact the underlying gate dielectric. Forming the gate electrode may include forming a polysilicon first gate electrode layer and forming an amorphous silicon layer over the polysilicon first gate electrode layer. Forming the second gate electrode layer may include forming a SiGe first sublayer and a polysilicon second sublayer.