Abstract: Converter systems are provided that use particular combinations of fixed and variable clock skewers to generate interleaved clock signals for the systems. These combinations have been found effective in accurately generating selectively-skewed clocks while simultaneously restricting the jitter that generally accompanies the skewing process.

Abstract: Converter systems are disclosed that use particular combinations of fixed and variable clock skewers to generate interleaved clock signals for the systems. These combinations have been found effective in accurately generating selectively-skewed clocks while simultaneously restricting the jitter that generally accompanies the skewing process.

Abstract: Comparator systems are provided that include cross-coupled transistors which respond to a differential network that receives an input signal. The systems further include a control transistor connected across the cross-coupled transistors and a bias network configured to apply a bias voltage to the control transistor that is substantially the voltage across two transistors which are each biased into saturation. It has been found that this bias during the systems' acquire phase substantially stabilizes the systems' gain over variations in their total environment and that this stabilization enhances the systems' performance.

Abstract: Time-interleaved signal converter systems are provided that multiplex respective digital sequences of system converters into an interleaved digital sequence before filtering each respective digital sequence with digital filters that apply respective filter coefficients to thereby reduce system degradation caused by converter timing skews. Use of the interleaved digital sequence in the filtering process substantially increases the system bandwidth from approximately one half of the converter sample rate RC to approximately one half of a greater system sample rate RS. Converter system embodiments are preferably configured to reduce large timing skews prior to filtering the interleaved digital sequence to obtain further reduction. This combined approach has been found to enhance interleaved system performance.

Abstract: Parallel analog-to-digital converter systems are provided in which converters are temporally interleaved. In particular, converters are partitioned into at least two converter groups which are assigned different respective group converter periods that are multiples of the system periods. With converters in each of the converter groups, respective samples are processed over that group's respective group converter period and the group converter periods of all converters are temporally shifted to process each of the samples with at least one of the converters.

Abstract: High-speed sampler methods and structures are provided to enhance the correlation between an input signal Sin and a corresponding sampler output voltage Vout. An input buffer is enabled during sampling time periods and disabled during holding time periods. In the sampling time periods, a sampling capacitor Cs is directly charged through the input buffer and the capacitor's bottom plate to a charge that corresponds to the input signal Sin. In the holding time periods, the disabled input buffer is isolated from the sampling capacitor Cs and a common-mode signal Scm is directly coupled to the capacitor's bottom plate to provide the output voltage Vout at the capacitor's top plate. Preferably, an output capacitor Co is coupled to the sampling capacitor Cs and charge from the sampling capacitor Cs is transferred to the output capacitor Co.

Abstract: A method of digital to analog conversion comprising switching binary weighted groups of first current sources of a first array of sources to an output in accordance with least significant bits of a digital input signal, driving the binary weighted groups with a driving current source selected from a second group of current sources in accordance with a counter value which is based on a value of most significant bits of the input signal added to a immediately preceding counter value, and driving an output with current sources which are addressable consecutively to the driving current source.

Abstract: Within the field of integrated circuits used in amplifiers, a structure and improved method for calibrating a switched capacitor gain stage wherein the time required to self-calibrate a switched capacitor gain stage and the associated structure are reduced. The invention utilizes only a single calibration step which is performed while the output of the amplifier being calibrated is monitored. Instead of utilizing a plurality of capacitors C.sub.a1 --C.sub.an each in parallel with groups of trim capacitors C.sub.T, a single capacitor C.sub.a is used and connected to switches S.sub.1a1 and S.sub.1b1. Further, instead of a group of trim capacitors C.sub.T being connected in parallel with the capacitor to be trimmed, each of plurality of trim capacitors C.sub.T1 -C.sub.TN is connected between the input to the operational amplifier and a respective corresponding switch S.sub.1a2 -S.sub.1aN to the input reference voltage node V.sub.b0. As well, switches S.sub.1b2 -S.sub.