Abstract: Described are techniques for presentation attack detection including a computer-implemented method of emitting a predetermined frequency pattern using at least one speaker communicatively coupled to a computer implementing a video-conference. The computer-implemented method further comprises collecting, by a camera communicatively coupled to the computer and overlapping with the emitting the predetermined frequency pattern, video data of a user engaged in the video-conference. The computer-implemented method further comprises determining that the video data is inconsistent with an expected response to the predetermined frequency pattern. The computer-implemented method further comprises generating an indication that the user engaged in the video-conference is performing a presentation attack.

Abstract: Described are techniques for presentation attack detection including a computer-implemented method of emitting a predetermined frequency pattern using at least one speaker communicatively coupled to a computer implementing a video-conference. The computer-implemented method further comprises collecting, by a camera communicatively coupled to the computer and overlapping with the emitting the predetermined frequency pattern, video data of a user engaged in the video-conference. The computer-implemented method further comprises determining that the video data is inconsistent with an expected response to the predetermined frequency pattern. The computer-implemented method further comprises generating an indication that the user engaged in the video-conference is performing a presentation attack.

Abstract: A method and an interfacing circuit are disclosed for transmitting data between a first clock domain operating at a first clock frequency C1 and a second clock domain operating at a second clock frequency C2. In accordance with this invention, data are transmitted from the first domain, through the interfacing circuitry, and to the second domain. Also, the interfacing circuitry includes a synchronization section that operates at a third frequency C3, which, in one embodiment, is greater than and a whole number multiple of C2. Preferably, C3 is an even whole number multiple of C2. In the preferred embodiment, a clock signal A is used to operate the second clock domain at frequency C2, and a clock signal B is used to operate the synchronization section of the interfacing circuitry at frequency C3, and clock signals A and B are source synchronized.

Abstract: A method an apparatus is provided to generate a gray code sequence from a sequence of binary values having a length “L”. Accordingly, one aspect of the present invention provides a circuit comprising a cycle flag toggle circuit configured to toggle a cycle flag between a first value and a second value, an intermediate value generator coupled to an output of the cycle flag toggle circuit configured to receive the binary value, and configured to generate an intermediate value from the cycle flag and the binary value, and a binary to gray converter coupled to an output of the intermediate value generator, configured to convert the intermediate value to a gray code.

Abstract: Methods for generating Gray count for an odd length sequence using a virtual space. More than one set of Gray codes can be generated for a given odd multiple virtual domains that assists in achieving more robust systems which are fault tolerant. Broadly contemplated herein is the use of a simple and elegant algorithm which is less complex and uses only an N-bit sequence.

Abstract: Methods for generating Gray count for an odd length sequence using a virtual space. More than one set of Gray codes can be generated for a given odd multiple virtual domains that assists in achieving more robust systems which are fault tolerant. Broadly contemplated herein is the use of a simple and elegant algorithm which is less complex and uses only an N-bit sequence.

Abstract: A method and an interfacing circuit are disclosed for transmitting data between a first clock domain operating at a first clock frequency C1 and a second clock domain operating at a second clock frequency C2. In accordance with this invention, data are transmitted from the first domain, through the interfacing circuitry, and to the second domain. Also, the interfacing circuitry includes a synchronization section that operates at a third frequency C3, which, in one embodiment, is greater than and a whole number multiple of C2. Preferably, C3 is an even whole number multiple of C2. In the preferred embodiment, a clock signal A is used to operate the second clock domain at frequency C2, and a clock signal B is used to operate the synchronization section of the interfacing circuitry at frequency C3, and clock signals A and B are source synchronized.

Abstract: Generating Gray sequences for non-standard sequence lengths to be used in cyclical sequences having L members. For binary members of the cyclical sequence having values less than L/2 an amount (C/2?L) the most significant bit is forced to a logical “1” to create intermediate binary members. For members greater than or equal to an amount (C/2?L) is added to the binary to create intermediate binaries. The intermediate binaries are then transformed to a Gray code sequence having a non-standard sequence length of L.