Patents by Inventor David Greenhill
David Greenhill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240131033Abstract: This invention relates to a method of treating damage to the central nervous system, comprising administering a pharmaceutically-effective amount of a CCR5 antagonist, and a pharmaceutically effective amount of an AQP4 antagonist, or pharmaceutically acceptable salts thereof.Type: ApplicationFiled: February 4, 2022Publication date: April 25, 2024Inventors: Roslyn Mary Bill, Stuart David Greenhill, Luke David Southan
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Patent number: 11475719Abstract: Systems and methods for integrating data related to aircraft operations such as data from flight logs, flight tracker, maintenance, connectivity, router into modules, for a specific aircraft that can be communicated to and displayed on a single device display in real-time. Systems and methods for integrating data related to aircraft operations into modules, that is both aircraft-specific (engine data, take-off and landing times) and personnel specific (i.e. crew scheduling, passenger manifestos), that includes a web-based interface which incorporates multiple data fields, and can display and communicate on devices, including but not limited to desktop computers, portable devices, such as smart phones, tablets and laptops.Type: GrantFiled: August 10, 2018Date of Patent: October 18, 2022Inventors: James Jensen, Jason Natwick, Greg Romano, Brian Rudloff, David Greenhill, Derek Donahue, Christopher Moore
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Patent number: 11334263Abstract: An integrated circuit device may cache configuration data to enable rapid configuration from fabric cache memory. The integrated circuit device may include programmable logic fabric having configuration memory and programmable logic elements controlled by the configuration memory, and sector-aligned memory apart from the programmable logic fabric. A first sector of the configuration memory may be programmed with first configuration data. The sector-aligned memory may include a first sector of sector-aligned memory that may cache the first configuration data while the configuration memory is programmed with the first configuration data a first time. A second sector of sector-aligned memory may cache second configuration data for a second sector of the configuration memory in parallel while the first sector of sector-aligned memory caches the first configuration data for the first sector of the configuration memory.Type: GrantFiled: January 11, 2018Date of Patent: May 17, 2022Assignee: Intel CorporationInventors: Scott J. Weber, David Greenhill, Sean R. Atsatt, Ravi Prakash Gutala, Aravind Raghavendra Dasu, Jun Pin Tan
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Publication number: 20190042127Abstract: An integrated circuit device may cache configuration data to enable rapid configuration from fabric cache memory. The integrated circuit device may include programmable logic fabric having configuration memory and programmable logic elements controlled by the configuration memory, and sector-aligned memory apart from the programmable logic fabric. A first sector of the configuration memory may be programmed with first configuration data. The sector-aligned memory may include a first sector of sector-aligned memory that may cache the first configuration data while the configuration memory is programmed with the first configuration data a first time. A second sector of sector-aligned memory may cache second configuration data for a second sector of the configuration memory in parallel while the first sector of sector-aligned memory caches the first configuration data for the first sector of the configuration memory.Type: ApplicationFiled: January 11, 2018Publication date: February 7, 2019Inventors: Scott J. Weber, David Greenhill, Sean R. Atsatt, Ravi Prakash Gutala, Aravind Raghavendra Dasu, Jun Pin Tan
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Patent number: 10049508Abstract: Systems and methods for integrating data related to aircraft operations such as data from flight logs, flight tracker, maintenance, connectivity, router into modules, for a specific aircraft that can be communicated to and displayed on a single device display in real-time. Systems and methods for integrating data related to aircraft operations into modules, that is both aircraft-specific (engine data, take-off and landing times) and personnel specific (i.e. crew scheduling, passenger manifestos), that includes a web-based interface which incorporates multiple data fields, and can display and communicate on devices, including but not limited to desktop computers, portable devices, such as smart phones, tablets and laptops.Type: GrantFiled: December 9, 2016Date of Patent: August 14, 2018Assignee: Satcom Direct, Inc.Inventors: James Jensen, Jason Natwick, Greg Romano, Brian Rudloff, David Greenhill, Derek Donahue, Christopher Moore
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Publication number: 20170124780Abstract: Systems and methods for integrating data related to aircraft operations such as data from flight logs, flight tracker, maintenance, connectivity, router into modules, for a specific aircraft that can be communicated to and displayed on a single device display in real-time. Systems and methods for integrating data related to aircraft operations into modules, that is both aircraft-specific (engine data, take-off and landing times) and personnel specific (i.e. crew scheduling, passenger manifestos), that includes a web-based interface which incorporates multiple data fields, and can display and communicate on devices, including but not limited to desktop computers, portable devices, such as smart phones, tablets and laptops.Type: ApplicationFiled: December 9, 2016Publication date: May 4, 2017Inventors: James Jensen, Jason Natwick, Greg Romano, Brian Rudloff, David Greenhill, Derek Donahue, Christopher Moore
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Patent number: 8648645Abstract: Disclosed is a digital voltage regulator system and method for mitigating voltage droop in an integrated circuit. If an unacceptable voltage droop is detected, the digital voltage regulator may take action to allow the power supply voltage to recover. A digital voltage regulator in accordance with embodiments discussed herein detects voltage droop by comparing a power supply voltage measurement with a threshold voltage. The threshold voltage may be calibrated based on power supply voltage measurements taken while the integrated circuit is operating.Type: GrantFiled: May 25, 2010Date of Patent: February 11, 2014Assignee: Oracle International CorporationInventors: Georgios Konstadinidis, Sudhakar Bobba, David Greenhill
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Patent number: 8283960Abstract: A digital voltage regulator including a dual rail delay chain having large size, feed forward cross-coupled inverters that interconnect the two rails. Stages of the delay chain include a dual-ended output that provides a data signal and a substantially simultaneous data complement signal to a flip-flop component associated with a sampling circuit. In use, the enhanced resolution delay chain and the reduced metastability window flop-flop increase the precision of the digital voltage regulator.Type: GrantFiled: April 27, 2009Date of Patent: October 9, 2012Assignee: Oracle America, Inc.Inventors: Hanh-Phuc Le, Robert P. Masleid, David Greenhill
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Publication number: 20120218034Abstract: A method and apparatus for power supply calibration to reduce voltage guardbands is disclosed. In one embodiment, an integrated circuit (IC) includes a voltage measurement unit configured to measure an operating voltage during a start-up procedure. The IC further includes a comparator configured to compare the measured operating voltage to a target voltage. The comparator is further configured to cause a change to a supply voltage (upon which the operating voltage is based) if the operating voltage is not within a target voltage range and to repeat the measurement of the operating voltage. If the operating voltage is within the target voltage range, the comparator is configured to inhibit further changes to the operating voltage.Type: ApplicationFiled: February 28, 2011Publication date: August 30, 2012Inventors: Sebastian Turullols, Ali Vahidsafa, David Greenhill
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Patent number: 8198931Abstract: A dual rail delay chain having cross-coupled inverters that interconnect the two rails. Delay chain embodiments include cross-coupled inverters that are part of a feed forward signal path between the two rails and are of a larger size than inverters associated with the two rails. The large size feed forward cross-coupled inverters contribute to an enhanced resolution of the delay chain.Type: GrantFiled: April 27, 2009Date of Patent: June 12, 2012Assignee: Oracle America, Inc.Inventors: Hanh-Phuc Le, Robert P. Masleid, David Greenhill
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Publication number: 20110291630Abstract: Disclosed is a digital voltage regulator system and method for mitigating voltage droop in an integrated circuit. If an unacceptable voltage droop is detected, the digital voltage regulator may take action to allow the power supply voltage to recover. A digital voltage regulator in accordance with embodiments discussed herein detects voltage droop by comparing a power supply voltage measurement with a threshold voltage. The threshold voltage may be calibrated based on power supply voltage measurements taken while the integrated circuit is operating.Type: ApplicationFiled: May 25, 2010Publication date: December 1, 2011Applicant: Oracle International CorporationInventors: Georgios Konstadinidis, Sudhakar Bobba, David Greenhill
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Patent number: 7872516Abstract: A pulse generator circuit. The pulse generator circuit includes a precharge circuit coupled to receive a clock signal alternating between a first logic level and a second logic level, a storage circuit having a storage node, wherein the precharge circuit is configured to precharge the storage node when the clock signal is at the first logic level, a logic circuit having an output, a first input node coupled to receive the clock signal, and a second input node coupled to the storage node and configured to produce a pulse at the second logic level responsive to the clock signal transitioning to the second logic level, and a discharge circuit configured to discharge the storage node at a predetermined delay time subsequent to the clock signal transitioning to the second logic level, wherein the output of the logic circuit transitions to the first logic level responsive to discharging the storage node.Type: GrantFiled: November 25, 2008Date of Patent: January 18, 2011Assignee: Oracle America, Inc.Inventors: Robert P Masleid, David Greenhill
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Publication number: 20100271099Abstract: A dual rail delay chain having cross-coupled inverters that interconnect the two rails. Delay chain embodiments include cross-coupled inverters that are part of a feed forward signal path between the two rails and are of a larger size than inverters associated with the two rails. The large size feed forward cross-coupled inverters contribute to an enhanced resolution of the delay chain.Type: ApplicationFiled: April 27, 2009Publication date: October 28, 2010Applicant: Sun Microsystems, Inc.Inventors: Hanh-Phuc Le, Robert P. Masleid, David Greenhill
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Publication number: 20100271100Abstract: A digital voltage regulator including a dual rail delay chain having large size, feed forward cross-coupled inverters that interconnect the two rails. Stages of the delay chain include a dual-ended output that provides a data signal and a substantially simultaneous data complement signal to a flip-flop component associated with a sampling circuit. In use, the enhanced resolution delay chain and the reduced metastability window flop-flop increase the precision of the digital voltage regulator.Type: ApplicationFiled: April 27, 2009Publication date: October 28, 2010Applicant: Sun Microsystems, Inc.Inventors: Hanh-Phuc Le, Robert P. Masleid, David Greenhill
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Publication number: 20100127749Abstract: A pulse generator circuit. The pulse generator circuit includes a precharge circuit coupled to receive a clock signal alternating between a first logic level and a second logic level, a storage circuit having a storage node, wherein the precharge circuit is configured to precharge the storage node when the clock signal is at the first logic level, a logic circuit having an output, a first input node coupled to receive the clock signal, and a second input node coupled to the storage node and configured to produce a pulse at the second logic level responsive to the clock signal transitioning to the second logic level, and a discharge circuit configured to discharge the storage node at a predetermined delay time subsequent to the clock signal transitioning to the second logic level, wherein the output of the logic circuit transitions to the first logic level responsive to discharging the storage node.Type: ApplicationFiled: November 25, 2008Publication date: May 27, 2010Inventors: Robert P. Masleid, David Greenhill
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Patent number: 7098501Abstract: A capacitor structure in a semiconductor device is provided. The capacitor structure includes a first power rail on a topmost level of the semiconductor device, and a second power rail on the topmost level of the semiconductor device. The capacitor structure also includes a dielectric layer disposed over at least a portion of one of the first power rail and the second power rail. The capacitor structure further includes a conductive layer disposed over and between the first power rail and the second power rail where the conductive layer is in electrical contact with the power rail not having the dielectric layer, and the conductive layer is disposed over the dielectric layer.Type: GrantFiled: February 5, 2003Date of Patent: August 29, 2006Assignee: Sun Microsystems, Inc.Inventors: Weiran Kong, Bernard Ho, David Greenhill, Sudhakar Bobba
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Publication number: 20050239947Abstract: The present invention provides a conductive polymeric composition comprising: (a) functionalized silver particles; (b) organic polymer resin; dispersed in (c) solvent wherein the silver particles are functionalized by least partially coated with a surfactant and heated at a temperature in the range of 100-400° C.Type: ApplicationFiled: February 22, 2005Publication date: October 27, 2005Inventor: David Greenhill
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Publication number: 20040150026Abstract: A capacitor structure in a semiconductor device is provided. The capacitor structure includes a first power rail on a topmost level of the semiconductor device, and a second power rail on the topmost level of the semiconductor device. The capacitor structure also includes a dielectric layer disposed over at least a portion of one of the first power rail and the second power rail. The capacitor structure further includes a conductive layer disposed over and between the first power rail and the second power rail where the conductive layer is in electrical contact with the power rail not having the dielectric layer, and the conductive layer is disposed over the dielectric layer.Type: ApplicationFiled: February 5, 2003Publication date: August 5, 2004Applicant: Sun Microsystems, Inc.Inventors: Weiran Kong, Bernard Ho, David Greenhill, Sudhakar Bobba
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Patent number: 6570407Abstract: A scannable latch for use within a circuit path of a series of one or more dynamic circuits is provided. The scannable latch provides both latch functionality during normal operation and scan test functionality during scan mode operation. Particularly, the scannable latch has a dynamic input stage and a shadow latch, where the dynamic input stage's primary function occurs during normal operations and where the shadow latch's primary function occurs during scan operations. The scannable latch also has an output gate operatively connected to the dynamic input stage and shadow latch.Type: GrantFiled: January 30, 2002Date of Patent: May 27, 2003Assignee: Sun Microsystems, Inc.Inventors: Junji Sugisawa, Larry Kan, David Greenhill, Joseph Siegel
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Patent number: 5668490Abstract: A flip-flop with scan capability includes a four switches, a master stage, a slave stage and a scan-out logic gate. The flip-flop can operate in a functional mode, and a scan mode and receives a clock signal, a data signal, a scan clock signal and a scan-in signal. The flip-flop enters the functional mode when the clock signal runs free and the scan clock signal is held constant. The first switch receives the data signal and provides the data signal to the master stage for storage during a first part of a clock cycle. During a second part of the clock cycle, the third switch, connected between the master stage and the slave stage, closes, providing the data stored in the master stage to the slave stage and outputted as a q output signal. The flip-flop enters the scan mode when the clock signal is held constant and the scan clock signal runs free. The first switch is controlled to stay open by the constant clock signal.Type: GrantFiled: May 1, 1996Date of Patent: September 16, 1997Assignee: Sun Microsystems, Inc.Inventors: Sundari S. Mitra, David Greenhill, Philip A. Ferolito