Abstract: A computing entity is described that obtains at least one inspection image of an at least partially fabricated product and causes the at least one inspection image to be processed by a product inspection engine. The product inspection engine includes a machine learning-trained model. The computing entity obtains an inspection result determined based on the processing of the at least one inspection image by the product inspection engine; identifies one or more training images stored in an image database based at least in part on the at least one inspection image; associates automatically generated labeling data with the one or more training images based at least in part on the inspection result determined by the processing of the at least one inspection image; and causes training of the product inspection engine using the one or more training images and the associated labeling data.

Abstract: A computing entity is described that obtains at least one inspection image of an at least partially fabricated product and causes the at least one inspection image to be processed by a product inspection engine. The product inspection engine includes a machine learning-trained model. The computing entity obtains an inspection result determined based on the processing of the at least one inspection image by the product inspection engine; identifies one or more training images stored in an image database based at least in part on the at least one inspection image; associates automatically generated labeling data with the one or more training images based at least in part on the inspection result determined by the processing of the at least one inspection image; and causes training of the product inspection engine using the one or more training images and the associated labeling data.

Abstract: When a chip, or manufactured integrate circuit, is found to have a portion that is defective, “floorsweeping” may be used to salvage the working portion of the chip. Floorsweeping involves downgrading, or turning off, the portion of the chip with the defect and then operating the remaining portion of the chip as a lower quality chip than the larger chip that was originally intended. In use, applications will then only use the active portion of the chip. However, the resulting lower quality chip will still have the same static leakage of the larger, non-defective chip. This leakage results from a voltage still being applied to the entire area of the larger chip, even though a portion of that area has been downgraded. The present disclosure provides a method for processing defective chips to form a smaller chip that avoids the excess static leakage associated with floorsweeping by physically removing the defective portion of the chip.

Abstract: An electrical machine, such as a dynamoelectric machine, includes a stator with teeth that define slots between the teeth to accommodate electrically conductive windings and a rotor inside the stator. The rotor has alternating polarity magnetic poles. The magnetic poles at the rotor outnumber the slots at the stator. The machine includes flux choking features, each of which extends along a circumferential path between one pair of adjacent teeth on the stator at an inner edge of the stator.

Abstract: Methods for forming asymmetric gate structures comprising spacer elements disposed on the opposed sides of a gate electrode and having a different width are disclosed. The asymmetric gate structures are employed to form an asymmetric design of a halo region and extension regions of a field effect transistor using a symmetric implantation scheme, or to further enhance the effectiveness of asymmetric implantation schemes. The transistor performance may be significantly enhanced for a given basic transistor architecture. In particular, a large overlap area may be created at the source side with a steep concentration gradient of the PN junction due to the provision of the halo region, whereas the drain overlap may be significantly reduced or may even be completely avoided to further enhance the transistor performance.

Abstract: Methods for forming asymmetric gate structures comprising spacer elements disposed on the opposed sides of a gate electrode and having a different width are disclosed. The asymmetric gate structures are employed to form an asymmetric design of a halo region and extension regions of a field effect transistor using a symmetric implantation scheme, or to further enhance the effectiveness of asymmetric implantation schemes. The transistor performance may be significantly enhanced for a given basic transistor architecture. In particular, a large overlap area may be created at the source side with a steep concentration gradient of the PN junction due to the provision of the halo region, whereas the drain overlap may be significantly reduced or may even be completely avoided to further enhance the transistor performance.

Abstract: The present invention describes a process for three-dimensional integration of semiconductor devices and a resulting device. The process combines low temperature wafer bonding methods with backside/substrate contact processing methods, preferably with silicon on insulator devices. The present invention utilizes, in an inventive fashion, low temperature bonding processes used for bonded silicon on insulator (SOI) wafer technology. This low temperature bonding technology is adopted for stacking several silicon layers on top of each other and building active transistors and other circuit elements in each one. The back-side/substrate contact processing methods allow the interconnection of the bonded SOI layers.

Abstract: The present invention describes a process for three-dimensional integration of semiconductor devices and a resulting device. The process combines low temperature wafer bonding methods with backside/substrate contact processing methods, preferably with silicon on insulator devices. The present invention utilizes, in an inventive fashion, low temperature bonding processes used for bonded silicon on insulator (SOI) wafer technology. This low temperature bonding technology is adopted for stacking several silicon layers on top of each other and building active transistors and other circuit elements in each one. The backside/substrate contact processing methods allow the interconnection of the bonded SOI layers.

Abstract: The present invention is directed toward a method for independently doping the gate and the source-drain regions of a semiconductor device. The method is initiated by the provision. of a substrate having isolation regions and a thin insulating layer. Over the substrate is formed a polysilicon layer which is doped with a first type of dopant at a first doping level. Over the polysilicon layer is formed a conducting layer of material that can withstand temperatures of 1000° C., and over the conducting layer is formed a blocking layer. The polysilicon layer, the conducting layer and the blocking layer are etched to form a gate stack. Source-drain regions are subsequently doped with a second type of dopant at a second doping level. Source-drain regions are activated in a 1000° C. heat cycle, and, subsequently, TiSi2 is formed on the source-drain regions. Contacts are then formed.

Abstract: A toner cartridge for supplying toner to a replenishment apparatus of an electrophotographic imaging device has an elongated cylindrical container filled with toner. The container has a longitudinal axis, an open end and a closed end. An end cap is adapted and arranged to close the open end and to accommodate relative rotational motion between the container and the end cap. The end cap has a flange portion defining an open end terminating in an end portion having an edge. An elastomeric seal is provided to effect a positive, relatively low-friction toner seal between a relatively rotating container and the end cap. The seal in an exemplary embodiment comprises an elastomeric band, which is sized properly to affix onto the outside diameter of the cap end portion, with a portion of the seal extending beyond the cap end portion.

Abstract: This invention relates to a planetary grinding or polishing machine wherein the outer ring gear, the upper platen, and the lower platen are independently rotatable in the clockwise or counterclockwise directions at variable speeds. Such grinding or polishing is especially useful in high precision finishing of aluminum, nickel plated, and ceramic substrates where uniform and non-uniform surface finishes are required from surface-to-surface in the workpiece.

Abstract: A solid state form of a dye-solution absorption filter is disclosed. Physical vapor depositable (i.e., evaporable) dyes are codeposited with a polyester matrix in a vacuum system to randomly disperse dye molecules in a solid dilutant. The dyes are selected to absorb at the wavelengths of interest. Dilution in a transparent matrix affords narrow band absorption and good out of band transmittance. Multilayer configurations allow absorption of a plurality of wavelengths. The filter coating conforms to curved and sharply contoured surfaces and layers only 10 microns thick afford very high absorptance.

Abstract: A solid state form of a dye-solution absorption filter is disclosed. Physical vapor depositable (i.e., evaporable) dyes are codeposited with a polyester matrix in a vacuum system to randomly disperse dye molecules in a solid dilutant. The dyes are selected to absorb at the wavelengths of interest. Dilution in a transparent matrix affords narrow band absorption and good out of band transmittance. Multilayer configurations allow absorption of a plurality of wavelengths. The filter coating conforms to curved and sharply contoured surfaces and layers only 10 microns thick afford very high absorptance.

Abstract: A solid state form of a dye-solution absorption filter is disclosed. Physical vapor depositable (i.e., evaporable) dyes are codeposited with a polyester matrix in a vacuum system to randomly disperse dye molecules in a solid dilutant. The dyes are selected to absorb at the wavelengths of interest. Dilution in a transparent matrix affords narrow band absorption and good out of band transmittance. Multilayer configurations allow absorption of a plurality of wavelengths. The filter coating conforms to curved and sharply contoured surfaces and layers only 10 microns thick afford very high absorptance.