Patents by Inventor David Grider

David Grider has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9184237
    Abstract: A vertical power transistor is monolithically packaged on a semiconductor die with gate buffer circuitry. The gate buffer circuitry is adapted to deliver a biasing voltage to a gate contact of the vertical power transistor for switching the device between an ON state and an OFF state. By monolithically packaging the gate buffer circuitry together with the vertical power transistor, parasitic inductance between the gate buffer circuitry and the gate of the vertical power transistor is minimized, thereby decreasing the switching time of the vertical power transistor and reducing switching noise.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: November 10, 2015
    Assignee: Cree, Inc.
    Inventors: Sei-Hyung Ryu, Craig Capell, Charlotte Jonas, David Grider
  • Publication number: 20140374773
    Abstract: A vertical power transistor is monolithically packaged on a semiconductor die with gate buffer circuitry. The gate buffer circuitry is adapted to deliver a biasing voltage to a gate contact of the vertical power transistor for switching the device between an ON state and an OFF state. By monolithically packaging the gate buffer circuitry together with the vertical power transistor, parasitic inductance between the gate buffer circuitry and the gate of the vertical power transistor is minimized, thereby decreasing the switching time of the vertical power transistor and reducing switching noise.
    Type: Application
    Filed: June 25, 2013
    Publication date: December 25, 2014
    Inventors: Sei-Hyung Ryu, Craig Capell, Charlotte Jonas, David Grider
  • Patent number: 7968391
    Abstract: A high voltage and high power gallium nitride (GaN) transistor structure is disclosed. A plurality of structural epitaxial layers including a GaN buffer layer is deposited on a substrate. A GaN termination layer is deposited on the plurality of structural epitaxial layers. The GaN termination layer is adapted to protect the plurality of structural epitaxial layers from surface reactions. The GaN termination layer is sufficiently thin to allow electrons to tunnel through the GaN termination layer. Electrical contacts are deposited on the GaN termination layer, thereby forming a high electron mobility transistor.
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: June 28, 2011
    Assignee: RF Micro Devices, Inc.
    Inventors: Joseph Smart, Brook Hosse, Shawn Gibb, David Grider, Jeffrey B. Shealy
  • Patent number: 7459356
    Abstract: The present invention relates to a high voltage and high power gallium nitride (GaN) transistor structure. In general, the GaN transistor structure includes a sub-buffer layer that serves to prevent injection of electrons into a substrate during high voltage operation, thereby improving performance of the GaN transistor structure during high voltage operation. Preferably, the sub-buffer layer is aluminum nitride, and the GaN transistor structure further includes a transitional layer, a GaN buffer layer, and an aluminum gallium nitride Schottky layer.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: December 2, 2008
    Assignee: RF Micro Devices, Inc.
    Inventors: Joseph Smart, Brook Hosse, Shawn Gibb, David Grider, Jeffrey Shealy
  • Patent number: 7408182
    Abstract: The present invention relates to passivation of a gallium nitride (GaN) structure before the GaN structure is removed from an epitaxial growth chamber. The GaN structure includes one or more structural epitaxial layers deposited on a substrate, and the passivation layer deposited on the structural epitaxial layers. In general, the passivation layer is a dielectric material deposited on the GaN structure that serves to passivate surface traps on the surface of the structural epitaxial layers. Preferably, the passivation layer is a dense, thermally deposited silicon nitride passivation layer.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: August 5, 2008
    Assignee: RF Micro Devices, Inc.
    Inventors: Joseph Smart, David Grider, Shawn Gibb, Brook Hosse, Jeffrey Shealy
  • Patent number: 7052942
    Abstract: The present invention relates to passivation of a gallium nitride (GaN) structure before the GaN structure is removed from an epitaxial growth chamber. The GaN structure includes one or more structural epitaxial layers deposited on a substrate, and the passivation layer deposited on the structural epitaxial layers. In general, the passivation layer is a dielectric material deposited on the GaN structure that serves to passivate surface traps on the surface of the structural epitaxial layers. Preferably, the passivation layer is a dense, thermally deposited silicon nitride passivation layer.
    Type: Grant
    Filed: October 20, 2003
    Date of Patent: May 30, 2006
    Assignee: RF Micro Devices, Inc.
    Inventors: Joseph Smart, David Grider, Shawn Gibb, Brook Hosse, Jeffrey Shealy
  • Patent number: 7033961
    Abstract: The present invention relates to an epitaxial structure having one or more structural epitaxial layers, including a gallium nitride (GaN) layer, which is deposited on a substrate, and a method of growing the epitaxial structure, wherein the structural epitaxial layers can be separated from the substrate. In general, a sacrificial epitaxial layer is deposited on the substrate between the substrate and the structural epitaxial layers, and the structural epitaxial layers are deposited on the sacrificial layer. After growth, the structural epitaxial layers are separated from the substrate by oxidizing the sacrificial layer. The structural epitaxial layers include a nucleation layer deposited on the sacrificial layer and a gallium nitride layer deposited on the nucleation layer. Optionally, the oxidation of the sacrificial layer may also oxidize the nucleation layer.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: April 25, 2006
    Assignee: RF Micro Devices, Inc.
    Inventors: Joseph Smart, Brook Hosse, Shawn Gibb, David Grider, Jeffrey B. Shealy
  • Patent number: 7026665
    Abstract: The present invention relates to a high voltage and high power gallium nitride (GaN) transistor structure. In general, the GaN transistor structure includes a sub-buffer layer that serves to prevent injection of electrons into a substrate during high voltage operation, thereby improving performance of the GaN transistor structure during high voltage operation. Preferably, the sub-buffer layer is aluminum nitride, and the GaN transistor structure further includes a transitional layer, a GaN buffer layer, and an aluminum gallium nitride Schottky layer.
    Type: Grant
    Filed: October 20, 2003
    Date of Patent: April 11, 2006
    Assignee: RF Micro Devices, Inc.
    Inventors: Joseph Smart, Brook Hosse, Shawn Gibb, David Grider, Jeffrey Shealy
  • Publication number: 20050194602
    Abstract: A method for fabricating a non-planar heterostructure field effect transistor using group III-nitride materials with consistent repeatable results is disclosed. The method provides a substrate on which at least one layer of semiconductor material is deposited. An AlN layer is deposited on the at least one layer of semiconductor material. A portion of the AlN layer is removed using a solvent to create a non-planar region with consistent and repeatable results. The at least one layer beneath the AlN layer is insoluble in the solvent and therefore acts as an etch stop, preventing any damage to the at least one layer beneath the AlN layer. Furthermore, should the AlN layer incur any surface damage as a result of the reactive ion etching, the damage will be removed when exposed to the solvent to create the non-planar region.
    Type: Application
    Filed: September 1, 2004
    Publication date: September 8, 2005
    Inventors: Jeong Moon, Paul Hashimoto, Wah Wong, David Grider
  • Publication number: 20050056293
    Abstract: A smoking article having reduced ignition propensity is disclosed. The smoking article includes a tobacco column, a wrapper surrounding the tobacco column and a filter element. The wrapper has a base permeability, an untreated area and a least one discrete area treated with a composition to reducing the base permeability. The discretely treated area interacts with a coal of a burning tobacco firecone as it advances to self-extinguish the smoking article. The composition of the treated area includes a permeability reducing substance, a burn rate retarding substance and a burn rate accelerating substance. Either the burn rate retarding substance or the burn rate accelerating substance acts as an organoleptic enhancing substance. In this way a smoker's experience when smoking either the at least one treated area or the untreated area is substantially the same.
    Type: Application
    Filed: October 26, 2004
    Publication date: March 17, 2005
    Inventors: Michael Zawadzki, Arthur Ihring, David Grider, Terry Jessup, David Williams