Abstract: A method for scheduling different combinations of jobs simultaneously running on a shared hardware platform is disclosed. Schedules may be created while executing the current set of jobs, for one or more possible sets of jobs that may occur after a change in the current set of jobs. In at least one embodiment, the present invention may be implemented in a SDR system where the jobs may correspond to radios in the SDR system. The possible combinations of radios that may occur after a change in the set of currently running radios may be determined at run time by adding or removing one radio at a time from the set of currently running radios.

Abstract: An apparatus for solving a function, such as a mathematical function, may be configured to minimize cost indicators associated with solving the function. Embodiments may be used to compute, in a fast and efficient way, the results of a given mathematical function f(x) and to execute the required operations on the best possible computational elements available within the target platform. Embodiments may exploit a mixture of calculation/evaluation methods that can be implemented on each computational element of the platform in order to approximate the desired function within the desired degree of accuracy and at a low computational cost. Associated methods and computer program products may also be provided.

Abstract: An apparatus for generating a cyclostationary extension for scheduling periodic software tasks may include a processor and a memory storing executable computer program code that causes the apparatus to at least perform operations including determining a time period including time periods associated with one or more radios. Each of the radios may include algorithms that are executable during respective time intervals of the time period. The computer program code may cause the apparatus to cyclically repeating each of the algorithms a number of times for the duration of the time period. In this regard, the algorithms may be executable a plurality of times during the time period. The computer program code may cause the apparatus to determine whether the algorithms are assignable to processors for execution during the respective time intervals based at least in part on a value. Corresponding computer program products and methods are also provided.

Abstract: The present invention relates to a method for performing calculation operations using a pipelined calculation device comprising a group of at least two pipeline stages. The pipeline stages comprise at least one data interface for input of data and at least one data interface for output of data. In the method, data for performing calculation operations is input to the device. Selective data processing is performed in the calculation device, wherein between at least one input data interface and at least one output data interface a selection is performed to connect at least one input data interface to at least one output data interface for routing data between at least one input data interface and at least one output data interface and for processing data according to the selection. The invention further relates to a system and a device in which the method is utilized.

Abstract: A signal processing method, receiver and equalizing method are provided. The receiver comprises an estimator estimating a channel coefficient matrix from a received signal, a first calculation unit determining a channel correlation matrix based on the channel coefficient matrix a converter converting the channel correlation matrix into a circulant matrix. A second calculation unit determines equalization filter coefficients by applying a first transform to the real parts of a first subset of the terms in the first column of the circulant matrix and by applying a second transform to the imaginary parts of a second subset of the terms in the first column of the circulant matrix. An equalizer equalizes the received signal by using the determined equalization filter coefficients.

Abstract: Subvector slices x(i,r,s) of a first vector x(i) are stored (e.g., in a CAM array) in a bit-parallel word-serial manner. For each of the stored subvector slices and in parallel on bits of said each subvector slice, an operation is executed that outputs a pre-calculated inner product result of the said bits and a second vector a. If the subvector slices x(i,r,s) of the first vector x(i) are initially stored in a bit-serial word-serial manner, there is a transform to store them in the bit-parallel word serial manner by copying relevant bits of each of the subvector slices from a 0th column of a content-addressable memory array to elements of a tags register and, for each kth iteration, shifting bits in the elements of the tags register by m positions and copying the shifted bits to a column of the CAM array. An associative processor outputs the pre-calculated inner product result in a distributed arithmetic manner.

Abstract: An apparatus for identifying techniques for solving functions may include a processor. The processor may be configured to identify a function and identify candidate techniques for solving the function. The processor may also be configured to separate a domain of the function into a plurality of domain intervals and determine respective cost indicators for each candidate technique as applied to each domain interval of the function. Further, the processor may be configured to select a technique for each domain interval based on the cost indicators; and provide for configuring an application processor to solve the function via the selected techniques and the respective domain intervals. Associated methods and computer program products may also be provided.

Abstract: A method for scheduling different combinations of jobs simultaneously running on a shared hardware platform is disclosed. Schedules may be created while executing the current set of jobs, for one or more possible sets of jobs that may occur after a change in the current set of jobs. In at least one embodiment, the present invention may be implemented in a SDR system where the jobs may correspond to radios in the SDR system. The possible combinations of radios that may occur after a change in the set of currently running radios may be determined at run time by adding or removing one radio at a time from the set of currently running radios.

Abstract: A current video block of a frame to be encoded comprises a set of first data values, and at least one other video block of another frame comprises a set of second data values. Data value pairs are formed of data values from said set of first data values and equal number of corresponding data values from said set of second data values. A combined comparison value is formed by defining comparison values, each of which is defined by using data values of one data value pair of said data value pairs. Said data value pairs are divided into at least two sub-sets of data value pairs each sub-set comprising equal number of data value pairs. The calculation of the comparison values is interlaced such that the calculation of comparison values of one sub-set of data value pairs is initiated in a time after initiating and before completing the calculation of comparison values of another sub-set of data value pairs.

Abstract: A signal processing method, receiver and equalizing method are provided. The receiver comprises an estimator estimating a channel coefficient matrix from a received signal, a first calculation unit determining a channel correlation matrix based on the channel coefficient matrix a converter converting the channel correlation matrix into a circulant matrix. A second calculation unit determines equalization filter coefficients by applying a first transform to the real parts of a first subset of the terms in the first column of the circulant matrix and by applying a second transform to the imaginary parts of a second subset of the terms in the first column of the circulant matrix. An equalizer equalizes the received signal by using the determined equalization filter coefficients.

Abstract: The disclosed embodiments relate to a microprocessor structure for performing a discrete wavelet transform operation. It uses a flowgraph representation of discrete wavelet transforms (DWTs) and wavelet packets. This representation is useful for developing efficient parallel algorithms and VLSI architectures. As examples, two DWT architectures for Haar wavelets and three architectures for Hadamard wavelets and wavelet packets are proposed with the efficiency (counted as the measure of the average utilization of basic processing elements) of approximately 100%. The proposed architectures are fast and provide excellent performance with respect to area-time characteristics. They are scalable, simple, regular,and free of long connections (depending on the length of input signal). The disclosed embodiments can be extended to inverse wavelet transforms.

Abstract: A method for performing video motion estimation in video encoding, in which a video signal consists of frames comprising blocks. In the method a combined comparison value is calculated between a current video block of a frame to be encoded and at least one other video block of another frame. The current video block of the frame to be encoded comprises a set of first data values, and the at least one other video block of another frame comprises a set of second data values. Data value pairs are formed of data values from the set of first data values and equal number of corresponding data values from the set of second data values. The combined comparison value is formed by defining comparison values, each of which is defined by using data values of one data value pair of the data value pairs. Further, at least one threshold value is defined, and it is determined whether the process for defining the combined comparison value can be terminated.

Abstract: A current video block of a frame to be encoded comprises a set of first data values, and at least one other video block of another frame comprises a set of second data values. Data value pairs are formed of data values from said set of first data values and equal number of corresponding data values from said set of second data values. A combined comparison value is formed by defining comparison values, each of which is defined by using data values of one data value pair of said data value pairs. Said data value pairs are divided into at least two sub-sets of data value pairs each sub-set comprising equal number of data value pairs. The calculation of the comparison values is interlaced such that the calculation of comparison values of one sub-set of data value pairs is initiated in a time after initiating and before completing the calculation of comparison values of another sub-set of data value pairs.

Abstract: A current video block of a frame to be encoded comprises a set of first data values, and at least one other video block of another frame comprises a set of second data values. Data value pairs are formed of data values from said set of first data values and equal number of corresponding data values from said set of second data values. A combined comparison value is formed by defining comparison values, each of which is defined by using data values of one data value pair of said data value pairs. Said data value pairs are divided into at least two sub-sets of data value pairs each sub-set comprising equal number of data value pairs. The calculation of the comparison values is interlaced such that the calculation of comparison values of one sub-set of data value pairs is initiated in a time after initiating and before completing the calculation of comparison values of another sub-set of data value pairs.

Abstract: A microprocessor structure for performing a discrete wavelet transform operation, said discrete wavelet transform operation comprising decomposition of an input signal comprising a vector of r×km input samples, r, k and m being non-zero positive integers, over a specified number of decomposition levels j, where j is an integer in the range 1 to J, starting from a first decomposition level and progressing to a final decomposition level, said microprocessor structure having a number of processing stages, each of said number of processing stages corresponding to a decomposition level j of the discrete wavelet transform operation and being implemented by a number of basic processing elements, the number of basic processing elements implemented in each of said processing stages decreasing by a factor of k from a decomposition level j to a decomposition level j+1.

Abstract: The present invention relates to a method for performing calculation operations using a pipelined calculation device comprising a group of at least two pipeline stages. The pipeline stages comprise at least one data interface for input of data and at least one data interface for output of data. In the method, data for performing calculation operations is input to the device. Selective data processing is performed in the calculation device, wherein between at least one input data interface and at least one output data interface a selection is performed to connect at least one input data interface to at least one output data interface for routing data between at least one input data interface and at least one output data interface and for processing data according to the selection. The invention further relates to a system and a device in which the method is utilized.

Abstract: The present invention relates to a method for performing video motion estimation in video encoding. The video signal consists of frames comprising blocks. In the method a combined comparison value is formed by using a current video block of a frame to be encoded and at least one other video block of another frame. Said current video block of the frame to be encoded comprises a set of first data values, and said at least one other video block of another frame comprises a set of second data values. In the method data value pairs are formed of data values from said set of first data values and equal number of corresponding data values from said set of second data values. Said combined comparison value is formed by defining comparison values, each of which is defined by using data values of one data value pair of said data value pairs. Said data value pairs are divided into at lest two sub-sets of data value pairs each sub-set comprising equal number of data value pairs.

Abstract: A microprocessor structure for performing a discrete wavelet transform operation, said discrete wavelet transform operation comprising decomposition of an input signal comprising a vector of r×km input samples, r, k and m being non-zero positive integers, over a specified number of decomposition levels j, where j is an integer in the range 1 to J, starting from a first decomposition level and progressing to a final decomposition level, said microprocessor structure having a number of processing stages, each of said number of processing stages corresponding to a decomposition level j of the discrete wavelet transform operation and being implemented by a number of basic processing elements, the number of basic processing elements implemented in each of said processing stages decreasing by a factor of k from a decomposition level j to a decomposition level j+1.

Abstract: The invention relates to a microprocessor structure for performing a discrete wavelet transform operation. It uses a flowgraph representation of discrete wavelet transforms (DWTs) and wavelet packets. This representation is useful for developing efficient parallel algorithms and VLSI architectures. As examples, two DWT architectures for Haar wavelets and three architectures for Hadamard wavelets and wavelet packets are proposed with the efficiency (counted as the measure of the average utilization of basic processing elements) of approximately 100%. The proposed architectures are fast and provide excellent performance with respect to area-time characteristics. They are scalable, simple, regular, and free of long connections (depending on the length of input signal). The invention can be extended to inverse wavelet transforms.

Abstract: The present invention relates to a method for performing video motion estimation in video encoding, in which video signal consists of frames comprising blocks. In the method a combined comparison value is calculated between a current video block of a frame to be encoded and at least one other video block of another frame. Said current video block of the frame to be encoded comprises a set of first data values, and said at least one other video block of another frame comprises a set of second data values. Data value pairs are formed of data values from said set of first data values and equal number of corresponding data values from said set of second data values. Said combined comparison value is formed by defining comparison values, each of which is defined by using data values of one data value pair of said data value pairs. Further, at least one threshold value is defined, and it is determined whether the process for defining said combined comparison value can be terminated.