Abstract: A method for launching a program application is provided. Here, configuration instructions are stored in a memory device and the configuration instructions are associated with multiple configurations. A configuration is selected from the multiple configurations when the memory device is coupled to a computing device. Thereafter, a configuration instruction associated with the configuration is retrieved from the memory device. The program application is launched and the configuration instruction is transmitted to the program application.

Abstract: A method for launching a program application is provided. Here, configuration instructions are stored in a memory device and the configuration instructions are associated with multiple configurations. A configuration is selected from the multiple configurations when the memory device is coupled to a computing device. Thereafter, a configuration instruction associated with the configuration is retrieved from the memory device. The program application is launched and the configuration instruction is transmitted to the program application.

Abstract: A computing device is provided. The computing device comprises a processor. The processor is configured to select a configuration from multiple configurations when the computing device is coupled to a memory device. The processor is further configured to retrieve a configuration instruction associated with the configuration from the memory device. In addition, the processor is configured to launch a program application associated with the configuration instruction and transmit the configuration instruction to the program application.

Abstract: System and method for testing differential signal crossover in high-speed electronic equipment. A preferred embodiment comprises a test circuit coupled to a device under test (DUT) and an automatic test equipment (ATE). The test circuit comprises a pair of window comparators coupled to a differential mode signal from the DUT, each window comparator configured to compare one of two signals making up the differential mode signal with a voltage boundary when enabled by an enable signal. The ATE is configured to provide clock signals to the test circuit and the DUT and to process data produced by the test circuit to determine if the differential signal crossover meets timing constraints. The test circuit uses undersampling to enable testing of high frequency signals without requiring an extremely high sampling rate.

Abstract: The present invention provides a system (100) that overcomes performance incongruities between a high-speed device (102) and commercial ATE (106). The system of the present invention provides an analog-to-analog sampler (104), having a clock input (118). The analog-to-analog sampler receives a first analog test signal (108) from the high-speed device, and converts it into a second analog test signal (116) at a desired rate, utilizing an analog-to-digital-to-analog conversion function (112) and a decimation function (114). The ATE system houses an analog capture component (120). The analog capture component has a clock input (122), and receives the second analog test signal for conversion into digital format. A series of clock signals (126) are generated from a common frequency reference source (124), to provide the necessary clock signals throughout the system.

Abstract: According to one embodiment of the invention, a method of sampling a signal is provided. The method includes receiving over a signal path an analog signal generated using a first clock signal by a first device. The method also includes sampling the analog signal using a second clock signal to generate a numeric representation of at least a portion of the analog signal. The frequencies of the first and the second clock signals differ from one another by a known amount. The method also includes communicating over the signal path the numeric representation for receipt by a second device. The signal path experiences loading and at least a majority of the loading of the signal path occurs between the sampler and the second device.

Abstract: Methods and systems for digital testing of semiconductor devices are disclosed. The inventions include testing modules (10) for use with automatic test equipment (ATE) 20 and device interface boards (32) in order to extend their capabilities to perform digital testing of semiconductor devices (18). Testing modules (10) disclosed include memory (12) and a test engine (14), which may be configured for digital testing according to further steps of the invention.

Abstract: A system and method for providing successive approximation, such as can be used by a successive approximation converter or by a coherent undersampling digitizer. The system comprising a memory having a successive approximation value and a comparison system configured to receive and amplify the difference between a test signal and the successive approximation value and to convert the amplified signal to a digital signal. A multi-bit analog to digital convert can be used to convert the amplified signal to a digital signal.