Patents by Inventor David Gunnarsson
David Gunnarsson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11924040Abstract: A system and a method for traffic management on a network. The method including: determining a desired intent for a network operator's traffic; determining a set of classes for a traffic flow through a link; determining a minimum and target bandwidth for each class in the set of class based on the desired intent; measure user score and bandwidth use for each class; allocate a bandwidth per class based on the minimum and target bandwidth and measured user score; and shape the traffic flow to the allocated bandwidth.Type: GrantFiled: August 16, 2021Date of Patent: March 5, 2024Inventors: Kamakshi Sridhar, Lars Anton Gunnarsson, Mostafa Mohamed Hassan, Alexander Havang, Matthew Lee Farmer, Roberto Lucarelli, Mark Daniel Yamada, Peter Thomas Salanki, Kenneth David Faiczak
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Patent number: 11226364Abstract: A testing device (100) is for electrically testing integrated circuits on a wafer (102). The testing device (100) includes a vacuum chamber (109), a chuck (101) for holding the wafer (102), a probe card (103) for electrically contacting the integrated circuits, and a radiation shield (107) arranged inside the vacuum chamber (109) and enclosing the chuck (101) and the probe card (103). In the testing device (100), the vacuum chamber (109) is provided with a gate valve (123), the radiation shield (107) is provided with a hatch (122), and the testing device (100) includes a wafer loading assembly (125) for loading the wafer (102) onto the chuck (101) through the gate valve (123) and the hatch (122).Type: GrantFiled: April 29, 2020Date of Patent: January 18, 2022Assignees: Afore Oy, Bluefors Cryogenics OyInventors: Aki Junes, Ari Kuukkala, Timo Salminen, Vesa Henttonen, Matti Manninen, David Gunnarsson, Leif Roschier
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Patent number: 11181574Abstract: The present invention provides a testing device for electrically testing integrated circuits on a wafer. The testing device comprises a vacuum chamber, a chuck for holding the wafer, a probe card for electrically contacting the integrated circuits, means for moving the chuck relative to the probe card, a first radiation shield arranged inside the vacuum chamber and enclosing the chuck and the probe card, and a cooling unit thermally connected to the first radiation shield. The means for moving the chuck relative to the probe card comprises a supporting column having a first end and a second end, the first end of the supporting column being attached to the chuck, and the first radiation shield comprises a first fixed part having a first aperture through which the supporting column is arranged to pass, and a first movable part that is attached to the supporting column and arranged to cover the first aperture.Type: GrantFiled: April 29, 2020Date of Patent: November 23, 2021Assignees: Afore Oy, Bluefors Cryogenics OyInventors: Aki Junes, Ari Kuukkala, Timo Salminen, Vesa Henttonen, Matti Manninen, David Gunnarsson, Leif Roschier
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Publication number: 20200348356Abstract: The present invention provides a testing device for electrically testing integrated circuits on a wafer. The testing device comprises a vacuum chamber, a chuck for holding the wafer, a probe card for electrically contacting the integrated circuits, and a radiation shield arranged inside the vacuum chamber and enclosing the chuck and the probe card. In the testing device, the vacuum chamber is provided with a gate valve, the radiation shield is provided with a hatch, and the testing device comprises a wafer loading assembly for loading the wafer onto the chuck through the gate valve and the hatch.Type: ApplicationFiled: April 29, 2020Publication date: November 5, 2020Applicants: Afore Oy, BlueFors Cryogenics OyInventors: Aki JUNES, Ari KUUKKALA, Timo SALMINEN, Vesa HENTTONEN, Matti MANNINEN, David GUNNARSSON, Leif ROSCHIER
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Publication number: 20200348357Abstract: The present invention provides a testing device for electrically testing integrated circuits on a wafer. The testing device comprises a vacuum chamber, a chuck for holding the wafer, a probe card for electrically contacting the integrated circuits, means for moving the chuck relative to the probe card, a first radiation shield arranged inside the vacuum chamber and enclosing the chuck and the probe card, and a cooling unit thermally connected to the first radiation shield. The means for moving the chuck relative to the probe card comprises a supporting column having a first end and a second end, the first end of the supporting column being attached to the chuck, and the first radiation shield comprises a first fixed part having a first aperture through which the supporting column is arranged to pass, and a first movable part that is attached to the supporting column and arranged to cover the first aperture.Type: ApplicationFiled: April 29, 2020Publication date: November 5, 2020Applicants: Afore Oy, BlueFors Cryogenics OyInventors: Aki Junes, Ari Kuukkala, Timo Salminen, Vesa Henttonen, Matti Manninen, David Gunnarsson, Leif Roschier
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Patent number: 9964446Abstract: A bolometer is described. A bolometer includes a superconductor-insulator-semiconductor-superconductor structure or a superconductor-insulator-semiconductor-insulator-superconductor structure. The semiconductor comprises an electron gas in a layer of silicon, germanium or silicon-germanium alloy in which valley degeneracy is at least partially lifted. The insulator or a one or both of the insulators may comprise a layer of dielectric material. The insulator or a one or both of the insulators may comprise a layer of non-degenerately doped semiconductor.Type: GrantFiled: November 4, 2014Date of Patent: May 8, 2018Assignee: The University of WarwickInventors: David Gunnarsson, Evan Parker, Martin Prest, Mika Prunnila, Terence Whall
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Publication number: 20160290868Abstract: A bolometer is described. A bolometer includes a superconductor-insulator-semiconductor-superconductor structure or a superconductor-insulator-semiconductor-insulator-superconductor structure. The semiconductor comprises an electron gas in a layer of silicon, germanium or silicon-germanium alloy in which valley degeneracy is at least partially lifted. The insulator or a one or both of the insulators may comprise a layer of dielectric material. The insulator or a one or both of the insulators may comprise a layer of non-degenerately doped semiconductor.Type: ApplicationFiled: November 4, 2014Publication date: October 6, 2016Applicants: The University of Warwick, VTT Technical Research Centre of FinlandInventors: David Gunnarsson, Evan Parker, Martin Prest, Mika Prunnila, Terence Whall