Patents by Inventor David Gwilt

David Gwilt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070174513
    Abstract: A buffer is disclosed for storing data being transferred using a plurality of control channels, a data item of said data being transferred between a data source and a data destination using one of said plurality of control channels, said buffer comprising: a data input port operable to receive said data being transferred using said plurality of control channels; a data output port operable to output data to be transferred using said plurality of control channels; and a data store operable to store data received from said data input port prior to it being output by said data output port, said data store comprising a plurality of storage locations each operable to store a data item, said storage locations being arranged in groups, a storage location being allocated to a group in dependence on the control channel that a data item that it stores is received from, such that each group comprises storage locations storing data items received from a same one of said plurality of control channels.
    Type: Application
    Filed: January 23, 2006
    Publication date: July 26, 2007
    Applicant: ARM Limited
    Inventors: Christopher Wrigley, David Gwilt
  • Publication number: 20070162651
    Abstract: The application discloses a direct memory access controller operable to control data transfer between a plurality of data source and data destination pairs comprising: at least one port operable to receive data from at least one data source and to output data to at least one data destination; and a channel operable to transfer data between said at least some of said plurality of data source and data destination pairs, said channel comprising registers operable to store data transfer control data, said data transfer control data comprising a source address of said data to be transferred, a destination address of said data to be transferred and control data, said data source address and said data destination address specifying said data source and data destination; wherein prior to a data transfer between a data source and data destination pair said direct memory access controller is operable to request data transfer control data corresponding to said data source and data destination pair from a memory and to s
    Type: Application
    Filed: December 15, 2006
    Publication date: July 12, 2007
    Applicant: ARM LIMITED
    Inventors: David Gwilt, Christopher Wrigley
  • Publication number: 20070055813
    Abstract: An integrated circuit and method of operating the integrated circuit to access external memory are provided. The integrated circuit comprises interconnect logic for coupling master logic units and slave logic units to enable transactions to be performed, each transaction comprising an address transfer from a master logic unit to a slave logic unit and one or more data transfers between that master logic unit and that slave logic unit. At least one master logic unit is operable when seeking to access data from an external memory to initiate a transaction by issuing the address transfer via the interconnect logic, the transaction having format information associated therewith used to format the one or more data transfers of the transaction for transfer over the interconnect logic. A memory controller acts as a slave logic unit for the transaction, and is coupled to the external memory via an external bus.
    Type: Application
    Filed: August 8, 2006
    Publication date: March 8, 2007
    Applicant: ARM Limited
    Inventors: Graeme Ingram, Spencer Saunders, David Gwilt
  • Publication number: 20050273543
    Abstract: A data processing system is provided with a bus having separate write channels W and read channels R via which bus transactions are made. Bus transaction buffers 34 are provided within the bus structure to buffer write requests, particularly so as to alleviate problems associated with relatively slow bus slaves. The bus transaction buffers 34 are responsive to the memory addresses associated with write requests and read requests which pass through them to identify those to the same memory address, or memory addresses within a predetermined range, so as to either ensure a strict correct ordering of those transactions, read to follow write, or to satisfy a read following a write with a buffered write data value and then flushing the read request such that it does not reach its final destination.
    Type: Application
    Filed: June 8, 2004
    Publication date: December 8, 2005
    Applicant: ARM LIMITED
    Inventors: Peter Middleton, David Gwilt, Ian Devereux, Bruce Mathewson, Antony Harris, Richard Grisenthwaite
  • Publication number: 20050138252
    Abstract: A data processing apparatus comprises a master device 150, 160, 170, 180, a slave device 110, 120, 130 and a communication bus 140 via which transaction requests are passed from master to slave. A transaction annotator of the master device generates transaction identifiers having a master identifier portion and a priority request portion. The slave device determines an order of servicing of transaction requests in dependence upon transaction ordering requests at least partially derived from the master identifier portions and in dependence upon priority values specified in the priority request portions.
    Type: Application
    Filed: December 23, 2003
    Publication date: June 23, 2005
    Applicant: ARM LIMITED
    Inventor: David Gwilt