Abstract: Methods, systems, and devices are disclosed for managing building power, in one aspect, a method for managing building power includes determining values for power usage of a heating, ventilation, or air conditioning (HVAC) system in one or more zones of a building, the values including a cost of power value, a comfort value, a weighting function between the cost of power value and the comfort value, or a thermal storage value, in which the determining the values is based on a plurality of parameters including a price of power, a time of use, a total power allocation, or random variables including weather and building occupancy factors, and determining a power level for a plurality of states based on the determined values, the plurality of states corresponding to different levels of power to operate the HVAC system in the one or more zones.

Abstract: The present disclosure provides methods and systems for managing power in a processor having multiple cores. In one implementation, a microarchitecture of a core within a general-purpose processor may include configurable lanes (horizontal slices through the pipeline) which can be powered on and off independently from each other within the core. An online optimization algorithm may determine within a reasonably small fraction of a time slice a combination of lanes within different cores of the processor to be powered on that optimizes performance under a power constraint budget for the workload running on the general-purpose processor. The online optimization algorithm may use an objective function based on response surface models constructed to fit to a set of sampled data obtained by running the workload on the general-purpose processor with multiple cores, without running the full workload. In other implementations, the power supply to lanes can be gated.

Abstract: Methods, systems, and devices are disclosed for managing building power, in one aspect, a method for managing building power includes determining values for power usage of a heating, ventilation, or air conditioning (HVAC) system in one or more zones of a building, the values including a cost of power value, a comfort value, a weighting function between the cost of power value and the comfort value, or a thermal storage value, in which the determining the values is based on a plurality of parameters including a price of power, a time of use, a total power allocation, or random variables including weather and building occupancy factors, and determining a power level for a plurality of states based on the determined values, the plurality of states corresponding to different levels of power to operate the HVAC system in the one or more zones.

Abstract: The present disclosure provides methods and systems for managing power in a processor having multiple cores. In one implementation, a microarchitecture of a core within a general-purpose processor may include configurable lanes (horizontal slices through the pipeline) which can be powered on and off independently from each other within the core. An online optimization algorithm may determine within a reasonably small fraction of a time slice a combination of lanes within different cores of the processor to be powered on that optimizes performance under a power constraint budget for the workload running on the general-purpose processor. The online optimization algorithm may use an objective function based on response surface models constructed to fit to a set of sampled data obtained by running the workload on the general-purpose processor with multiple cores, without running the full workload. In other implementations, the power supply to lanes can be gated.

Abstract: A method and structure of reducing power consumption in a microprocessor includes at least one storage structure in which the activity of the storage structure is dynamically measured and the size of the structure is controlled based on the activity. The storage structure includes a plurality of blocks, and the size of the structure is controlled in units of block size, based on activity measured in the blocks. An exemplary embodiment is an adaptive out-of-order queue.

Abstract: A method and structure of reducing power consumption in a microprocessor includes at least one storage structure in which the activity of the storage structure is dynamically measured and the size of the structure is controlled based on the activity. The storage structure includes a plurality of blocks, and the size of the structure is controlled in units of block size, based on activity measured in the blocks. An exemplary embodiment is an adaptive out-of-order queue.

Abstract: A complexity-adaptive hardware/software system and method for a microprocessor to execute any of a plurality of diverse applications according to a predetermined instruction set architecture. The system includes dynamic hardware structures and configurable clocking system of the microprocessor for executing any particular application among the plurality of diverse applications, the dynamic hardware structures and configurable clocking system being adaptable to be organized in any of a plurality of potential configurations which are selectable according to the particular application to be executed. Configuration control is performed in response to the particular application to be executed, the instruction set architecture, and the potential configurations in which the dynamic hardware structures and configurable clocking system may be organized.

Abstract: A method and apparatus for detecting an improper connection of one or more cables to signal a cable misconnection error. On a board at one end of the cable there is provided a transmit circuit unique to one of the pins or sockets of the connector and at the other end of the cable at an opposite board there is provided a receive circuit that, when the cable is properly connected, receives the signal from the transmit circuit. A misconnection of the cable eliminates the signal from the transmit circuit thus signaling an error at the receive circuit. In addition, semi-dedicated connector positions are also employed so as to assure a detection of a number of different misconnections of the cable, particularly in a multi-cable system.

Abstract: The invention comprises a combined hardware and software method and apparatus for determining the size of memory located on a memory card inserted in the slot of a memory backplane of a computer system. The method and apparatus also provides a means for selecting the memory card which contains a requested memory location. Each memory slot has associated therewith a multibit code which indicates the size of the memory installed in the associated slot. The code from each slot is hardwired to the system memory controller which, given the codes can, as part of its memory initialization route, scan these bits and decode them in order to determine the amount of memory installed in each slot of the memory backplane.Each slot is further provided with an X-bit starting address which uniquely defines the lowest address available from the board inserted in the associated slot. The starting address from each slot is compared with the leftmost X-bits of the currently requested memory address.

Abstract: The invention comprises a system bus apparatus and method for a multi-arm, multiprocessor computer system having a main memory and localized buffer cache memories at each processor. Each block of data in a cache includes tag bits which identifies the condition of the data block in relation to the corresponding data in main memory and other caches. The system bus (SYSBUS) comprises three subparts; 1) a MESSAGE/DATA bus, 2) a REQUEST/GRANT bus and 3) a BCU bus. The MESSAGE/DATA bus is coupled to every device on the system and is used for transferring messages, data and addresses. The REQUEST/GRANT bus couples between every device on an arm of the system and that arm's bus control unit (BCU). The BCU bus couples between the various BCUs.

Abstract: A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration.

Abstract: A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration.